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authorMorgan Jang <Morgan_Jang@wiwynn.com>2020-05-25 12:23:59 +0800
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2020-07-16 13:07:31 +0000
commitb29d16fc8a1e15a9a5e7f5b389019b7593d42d02 (patch)
treec4b732fc6dd19f0a9b67f48eda158bc22b456572 /src/mainboard/ocp
parentb8d0d089b307a8e40f12af82d0191d52f8752b37 (diff)
downloadcoreboot-b29d16fc8a1e15a9a5e7f5b389019b7593d42d02.tar.xz
mb/ocp/deltalake: Config PCH PCIe ports in devicetree
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected. Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/mainboard/ocp')
-rw-r--r--src/mainboard/ocp/deltalake/devicetree.cb6
-rw-r--r--src/mainboard/ocp/deltalake/romstage.c15
2 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb
index f1b201d5f4..cc17e06f6c 100644
--- a/src/mainboard/ocp/deltalake/devicetree.cb
+++ b/src/mainboard/ocp/deltalake/devicetree.cb
@@ -39,6 +39,12 @@ chip soc/intel/xeon_sp/cpx
register "gen1_dec" = "0x00fc0601" # BIC in-band update support
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+ # configure PCH PCIe port
+ register "pch_pci_port[8]" = "{
+ .ForceEnable = 0x1,
+ .PortLinkSpeed = PcieAuto,
+ }"
+
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c
index 9ce06ad616..2c8dc5efa2 100644
--- a/src/mainboard/ocp/deltalake/romstage.c
+++ b/src/mainboard/ocp/deltalake/romstage.c
@@ -7,6 +7,7 @@
#include <FspmUpd.h>
#include <soc/romstage.h>
+#include "chip.h"
#include "ipmi.h"
#include "vpd.h"
@@ -74,7 +75,21 @@ static void mainboard_config_gpios(FSPM_UPD *mupd)
static void mainboard_config_iio(FSPM_UPD *mupd)
{
+ uint8_t index;
+ const config_t *config = config_of_soc();
+
oem_update_iio(mupd);
+
+ for (index = 0; index < MAX_PCH_PCIE_PORT; index++) {
+ mupd->FspmConfig.PchPcieForceEnable[index] =
+ config->pch_pci_port[index].ForceEnable;
+ mupd->FspmConfig.PchPciePortLinkSpeed[index] =
+ config->pch_pci_port[index].PortLinkSpeed;
+ }
+
+ mupd->FspmConfig.PchPcieRootPortFunctionSwap = 0x00;
+ /* The default value is 0XFF in FSP, set it to 0xFE by platform */
+ mupd->FspmConfig.PchPciePllSsc = 0xFE;
}
void mainboard_memory_init_params(FSPM_UPD *mupd)