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author | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-18 16:36:58 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-18 16:36:58 +0000 |
commit | df46cb205d57a91aa0fff142b2dd951e7731731b (patch) | |
tree | e3a0c5d526b6abbc57ab2d6ef4ba3b27d17ab788 /src/mainboard/olpc/rev_a/failover.c | |
parent | ea9db56d0e78499faf38a5d8e0c2125275c69ef2 (diff) | |
download | coreboot-df46cb205d57a91aa0fff142b2dd951e7731731b.tar.xz |
added the olpc target and support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/olpc/rev_a/failover.c')
-rw-r--r-- | src/mainboard/olpc/rev_a/failover.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/olpc/rev_a/failover.c b/src/mainboard/olpc/rev_a/failover.c new file mode 100644 index 0000000000..bdcb9eaed2 --- /dev/null +++ b/src/mainboard/olpc/rev_a/failover.c @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} |