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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-03 09:16:10 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 10:15:16 +0000 |
| commit | 3b452e0a797b54a05b97725f4e4e320c51098754 (patch) | |
| tree | 6cebd0c98dd87522f32a6179051673ae2225e17c /src/mainboard/packardbell/ms2290 | |
| parent | cea4fd9bb059dab2a0c10b48b1c645807665eec2 (diff) | |
| download | coreboot-3b452e0a797b54a05b97725f4e4e320c51098754.tar.xz | |
nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak
This change does the following:
- Move PCH init code from the common romstage to sb code, this allows
for easier reuse in bootblock
- Provide a common minimal LPC io decode setup, mainboards can
override this in the mainboard_lpc_init if required
- Set up LPC generic IO decode up in romstage based on devicetree
settings
- Remove the ramstage LPC generic IO decode from ramstage as this is
now done in romstage.c
- Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as
this is already done in the bootblock.
Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/packardbell/ms2290')
| -rw-r--r-- | src/mainboard/packardbell/ms2290/romstage.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index b25676bf53..61e14f20e3 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -24,23 +24,6 @@ void mainboard_lpc_init(void) { - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); } /* Seems copied from Lenovo Thinkpad x201, might be wrong */ |