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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 13:42:22 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-06-17 15:37:46 +0000 |
| commit | d37a5bc29ec0f69fad55e3bfb6f6aeb7e1027607 (patch) | |
| tree | c686c2a04224fd3a5c2a0cb6d96269bc80266c18 /src/mainboard/pcengines/alix1c | |
| parent | df946b8696731cda45a7e37e934307c3153b824f (diff) | |
| download | coreboot-d37a5bc29ec0f69fad55e3bfb6f6aeb7e1027607.tar.xz | |
mb/pcengines: Remove unneeded includes and dead code
Fix coding style.
Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/pcengines/alix1c')
| -rw-r--r-- | src/mainboard/pcengines/alix1c/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/pcengines/alix1c/irq_tables.c | 21 |
2 files changed, 11 insertions, 14 deletions
diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 8cb8dd3b03..5b4e603f18 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/lx device domain 0 on - device pci 1.0 on end + device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK @@ -25,7 +25,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + device pci f.0 on # ISA Bridge chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c index 89ac717df0..029624441d 100644 --- a/src/mainboard/pcengines/alix1c/irq_tables.c +++ b/src/mainboard/pcengines/alix1c/irq_tables.c @@ -14,9 +14,6 @@ */ #include <arch/pirq_routing.h> -#include <console/console.h> -#include <arch/io.h> -#include "southbridge/amd/cs5536/cs5536.h" /* Platform IRQs */ #define PIRQA 11 @@ -53,15 +50,15 @@ * * The only devices that interrupt are: * - * What Device IRQ PIN PIN WIRED TO + * What Device IRQ PIN PIN WIRED TO * ------------------------------------------------- - * AES 00:01.2 0a 01 A A - * 3VPCI 00:0c.0 0a 01 A A - * eth0 00:0d.0 0b 01 A B - * mpci 00:0e.0 0a 01 A A - * usb 00:0f.3 0b 02 B B - * usb 00:0f.4 0b 04 D D - * usb 00:0f.5 0b 04 D D + * AES 00:01.2 0a 01 A A + * 3VPCI 00:0c.0 0a 01 A A + * eth0 00:0d.0 0b 01 A B + * mpci 00:0e.0 0a 01 A A + * usb 00:0f.3 0b 02 B B + * usb 00:0f.4 0b 04 D D + * usb 00:0f.5 0b 04 D D * * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B. */ @@ -71,7 +68,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ 0x100B, /* Vendor */ 0x002B, /* Device */ |