More kconfig:

AMD LX
AMD SC520
boards by iei, pcengines, technexion, technologic, thomson

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 79 insertions, 0 deletions

diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig
new file mode 100644
index 0000000000..ae56c97bd2
--- /dev/null
+++ b/src/mainboard/pcengines/alix1c/Kconfig
@@ -0,0 +1,48 @@
+config BOARD_PCENGINES_ALIX1C
+	bool "alix.1c"
+	select ARCH_X86
+	select CPU_AMD_LX
+	select NORTHBRIDGE_AMD_LX
+	select SOUTHBRIDGE_AMD_CS5536
+	select SUPERIO_WINBOND_W83627HF
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+	select USE_DCACHE_RAM
+	select USE_PRINTK_IN_CAR
+
+config MAINBOARD_DIR
+	string
+	default pcengines/alix1c 
+	depends on BOARD_PCENGINES_ALIX1C
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ALIX.1C"
+	depends on BOARD_PCENGINES_ALIX1C
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_PCENGINES_ALIX1C
+
+config IRQ_SLOT_COUNT
+	int
+	default 5
+	depends on BOARD_PCENGINES_ALIX1C
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+	depends on BOARD_PCENGINES_ALIX1C
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_PCENGINES_ALIX1C
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_PCENGINES_ALIX1C
diff --git a/src/mainboard/pcengines/alix1c/Makefile.inc b/src/mainboard/pcengines/alix1c/Makefile.inc
new file mode 100644
index 0000000000..90b154a4e1
--- /dev/null
+++ b/src/mainboard/pcengines/alix1c/Makefile.inc
@@ -0,0 +1,31 @@
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+