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authorStefan Reinauer <stepan@coresystems.de>2010-04-21 20:06:10 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-21 20:06:10 +0000
commit9839cbd53fdcfcee52c406d9f52af924192e618d (patch)
treea38daaa0b545aaf36a7ad5f5df9dfe73e08d97da /src/mainboard/pcengines/alix1c
parentcf036d1266d7ec307aac437105b094acbc9681ec (diff)
downloadcoreboot-9839cbd53fdcfcee52c406d9f52af924192e618d.tar.xz
* clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M) * call void main(unsigned long bist) except void cache_as_ram_main(void) on Geode LX (as we do on almost all other platforms now) * Unify Geode LX MSR setup (will bring most non-working LX targets back to life) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/pcengines/alix1c')
-rw-r--r--src/mainboard/pcengines/alix1c/romstage.c24
1 files changed, 5 insertions, 19 deletions
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index c4a9cc98e5..a9b6db5a6c 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -115,31 +115,14 @@ static u8 spd_read_byte(u8 device, u8 address)
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
- msr_t msr;
-
- /* Setup access to the MC for under 1MB. Note MC not setup yet. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x10010000;
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff00;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff00;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
/** Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {0x50}},
@@ -161,6 +144,9 @@ void cache_as_ram_main(void)
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();