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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-11 17:22:23 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-23 21:34:55 +0100 |
| commit | 780935687d74f89a25a9c58952314be6af61c348 (patch) | |
| tree | 193897842085f03675cb6b97e1f9ca523abb7a83 /src/mainboard/pcengines/apu1/Makefile.inc | |
| parent | 8c190f3518d504d904692e93e7881c379b89f542 (diff) | |
| download | coreboot-780935687d74f89a25a9c58952314be6af61c348.tar.xz | |
pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/Makefile.inc')
| -rw-r--r-- | src/mainboard/pcengines/apu1/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index 749a6ad144..3695daa470 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -28,10 +28,12 @@ endif romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c +romstage-y += gpio_ftns.c ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ramstage-y += gpio_ftns.c ## DIMM SPD for on-board memory SPD_BIN = $(obj)/spd.bin |