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authorMichał Żygowski <michal.zygowski@3mdeb.com>2018-12-21 11:46:09 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-16 13:21:43 +0000
commit37d4ffb0a56bc127111c9f10ffe31e3a55e133ee (patch)
treed4cdf7abb5a3c65b24223d6783f41f61bdbbe7c2 /src/mainboard/pcengines/apu1/devicetree.cb
parent760970fb38157fc9023a3d71efaa8585bbdc9d7b (diff)
downloadcoreboot-37d4ffb0a56bc127111c9f10ffe31e3a55e133ee.tar.xz
src/mainboard/pcengines/apu1: Enable LPC TPM
PC Engines apu1 has a 20 pin LPC header that allows connection of external TPM module. Add necessary Kconfig option and devicetree entry for TPM. Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/30354 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/pcengines/apu1/devicetree.cb')
-rw-r--r--src/mainboard/pcengines/apu1/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 6af6d2e6de..2e8b8f4cfd 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -70,6 +70,9 @@ chip northbridge/amd/agesa/family14/root_complex
device pnp 2e.607 off end
device pnp 2e.e off end
end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end # LPC TPM
end #LPC
device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1
device pci 14.5 off end # OHCI FS/LS USB