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| author | Felix Held <felix-coreboot@felixheld.de> | 2015-11-06 18:31:01 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-19 02:43:12 +0100 |
| commit | b06015b92ec0a44646d18ec32f2cb333e965e616 (patch) | |
| tree | 8eb4be8e7ed74adf4fc5e9b83a5d7a2176e7f06d /src/mainboard/pcengines/apu1/mainboard.c | |
| parent | 1455437c9e010bcc617c5927e18cf1cb3b02c82f (diff) | |
| download | coreboot-b06015b92ec0a44646d18ec32f2cb333e965e616.tar.xz | |
pcengines/apu1: disable unused clock outputs
disable unconnected FCH clock outputs to save some power
Change-Id: Ib3efebb8656392d58d762c23827168017d273de8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12082
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/mainboard.c')
| -rw-r--r-- | src/mainboard/pcengines/apu1/mainboard.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index f80f24ec87..82cf9921a5 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -183,6 +183,18 @@ static void mainboard_enable(device_t dev) config_gpio_mux(); + /* Power off unused clock pins of GPP PCIe devices */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + /* GPP CLK0-2 are connected to the 3 ethernet chips + * GPP CLK3-4 are connected to the miniPCIe slots */ + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0xFF); + /* GPP CLK5 is only connected to test pads -> disable */ + write8(misc_mem_clk_cntrl + 2, 0x0F); + /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } |