diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-11 22:53:19 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-19 14:46:58 +0200 |
| commit | 017c2150d4a528c58a454705db74210477623a5f (patch) | |
| tree | d26524851cb6d57a48dc951e1a160904edc995d6 /src/mainboard/pcengines/apu1/mainboard.c | |
| parent | 58d5e21851ced6b475a87e3a4114b2c7e1125921 (diff) | |
| download | coreboot-017c2150d4a528c58a454705db74210477623a5f.tar.xz | |
pcengines/apu1: Add switch between UART and GPIO modes
These are alternative customer options connected to J19 header.
We need to avoid modifying devicetree.cb, so we fix devicetree
for the super-io device-enables at runtime instead.
Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/mainboard.c')
| -rw-r--r-- | src/mainboard/pcengines/apu1/mainboard.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 3b8541cae1..f49059d871 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -33,6 +33,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" void set_pcie_reset(void); @@ -135,6 +136,30 @@ static void pirq_setup(void) picr_data_ptr = mainboard_picr_data; } +/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit + * once configuration file format for SPI flash storage is complete. + */ +#define SIO_PORT 0x2e + +static void config_gpio_mux(void) +{ + struct device *uart, *gpio; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); + if (uart) + uart->enabled = CONFIG_PINMUX_UART_C; + if (gpio) + gpio->enabled = CONFIG_PINMUX_GPIO0; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); + if (uart) + uart->enabled = CONFIG_PINMUX_UART_D; + if (gpio) + gpio->enabled = CONFIG_PINMUX_GPIO1; +} + /** * TODO * SB CIMx callback @@ -158,6 +183,8 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + config_gpio_mux(); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } |