diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-10-14 16:03:56 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-10-15 12:08:42 +0000 |
| commit | c82ab0adf568cab2e899e34715e1d07a37ff3ebe (patch) | |
| tree | c87f5246d3b9395c06fb9495b77025438946d559 /src/mainboard/pcengines/apu1 | |
| parent | f50603176b579632d558a43166980ec2883a7017 (diff) | |
| download | coreboot-c82ab0adf568cab2e899e34715e1d07a37ff3ebe.tar.xz | |
pcengines/apu1: Fix SPD for 4GB model
Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.
Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/pcengines/apu1')
| -rw-r--r-- | src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex index 4af1bf8fe7..876ee649a2 100644 --- a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex +++ b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex @@ -127,7 +127,8 @@ # 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB # 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB # 0x500 = 160ns - for 2 Gigabit chips -00 05 +# 0x820 = 260ns - for 4 Gigabit chips +20 08 # 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) # 0x3c = 7.5 ns - All DDR3 SDRAM speed bins |