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authorPiotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>2020-01-08 15:06:26 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-01-15 18:54:40 +0000
commit941c9ac07495482a8d3d14a345ca99d51cf1f2b3 (patch)
treefe8f2feeaa4260cd2605b6410cd3f82f78f512a1 /src/mainboard/pcengines/apu1
parentb52f7c7c468e0456a126b88a84f6568b873a5ae0 (diff)
downloadcoreboot-941c9ac07495482a8d3d14a345ca99d51cf1f2b3.tar.xz
mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset
LDN 0xf keeps registers with open-drain configuration of the GPIO. Enabling the LDN is required for proper GPIO soft reset operation by the SuperIO driver. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/pcengines/apu1')
-rw-r--r--src/mainboard/pcengines/apu1/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 2e8b8f4cfd..d7c7952045 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -63,12 +63,12 @@ chip northbridge/amd/agesa/family14/root_complex
irq 0x70 = 3
end
device pnp 2e.8 off end
- device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 off end
device pnp 2e.107 off end
device pnp 2e.607 off end
device pnp 2e.e off end
+ device pnp 2e.f on end
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end