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authorPiotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>2020-05-21 17:48:12 +0200
committerMichał Żygowski <michal.zygowski@3mdeb.com>2020-05-22 09:41:24 +0000
commitaf90a1e6afd93bb4c42393ebd9a47b21e2222737 (patch)
treebd86ee85de8aa201f515d7c05cdf15674793809f /src/mainboard/pcengines/apu1
parentbe698de76e102fd7801444a04343c4bfbad1ff2a (diff)
downloadcoreboot-af90a1e6afd93bb4c42393ebd9a47b21e2222737.tar.xz
mb/pcengines/apu1/platform_cfg.h: Unset UsbRxMode to avoid platform reset issue
On PC Engines apu1 there were issues with cold reset. Platform hangs in boot path after performing reset using CF9h. CB:10549 (amd/sb800: Make UsbRxMode per-board customizable) mentions a similar issue, and added a configuration macro for it. That error is also described in AMD SB800 Family Product Errata, section 15 USB Resets Asynchronously With Port CF9h Hard Reset. This workaround simply non-execute USB configuration during boot and hence no reset via CF9h is done. TEST=perform multiple cold resets and see if platform boots Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Change-Id: Ie6cebcfc4b77e121ef44a25fa81377eb5e1f0644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41627 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/pcengines/apu1')
-rw-r--r--src/mainboard/pcengines/apu1/platform_cfg.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h
index 2f5c56c0da..63a3d5a7cb 100644
--- a/src/mainboard/pcengines/apu1/platform_cfg.h
+++ b/src/mainboard/pcengines/apu1/platform_cfg.h
@@ -212,4 +212,18 @@
*/
#define FADT_PM_PROFILE 1
+/**
+ * @def USB_RX_MODE
+ * 0x00 - leave Cg2Pll voltage at default value (1.222V)
+ * 0x01 - lower Cg2Pll voltage to 1.1V
+ *
+ * Workaround for reset issues via outb(0x6, 0xcf9).
+ * For details check:
+ * AMD SB800 Family Product Errata,
+ * Section 15. USB Resets Asynchronously With Port CF9h Hard Reset
+ *
+ */
+
+#define USB_RX_MODE 0x00
+
#endif /* _PLATFORM_CFG_H_ */