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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2018-11-22 11:13:31 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 15:08:38 +0000 |
| commit | efa022db501de6d8dcd4a76e74d0f23a1ffd9412 (patch) | |
| tree | 74941243f3482c88a0806ba0ece45d28dbb0f0db /src/mainboard/pcengines/apu1 | |
| parent | 88521881133e62d8f3298388faa718efabc9107a (diff) | |
| download | coreboot-efa022db501de6d8dcd4a76e74d0f23a1ffd9412.tar.xz | |
mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2
Enable COM2 port on SuperIO if UART index is 1. This change allows
to use full RS232 COM1 port for different purposes when COM2 is selected
as main port.
TEST=flash coreboot with console on COM2 and observer output with UBS-TTL
converter connected to COM2 header on PC Engines apu1
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1')
| -rw-r--r-- | src/mainboard/pcengines/apu1/bootblock.c | 8 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu1/romstage.c | 5 |
2 files changed, 6 insertions, 7 deletions
diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c index 2d34cba3bf..dc9f87d905 100644 --- a/src/mainboard/pcengines/apu1/bootblock.c +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -17,9 +17,13 @@ #include <superio/nuvoton/nct5104d/nct5104d.h> #define SIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) void bootblock_mainboard_early_init(void) { - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + if (CONFIG_UART_FOR_CONSOLE == 1) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 20a6318a46..df91b04c0a 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -17,15 +17,10 @@ #include <amdblocks/acpimmio.h> #include <northbridge/amd/agesa/state_machine.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" #include <SB800.h> #include <sb_cimx.h> -#define SIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) - static void early_lpc_init(void) { u32 mmio_base; |