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authorPiotr Król <piotr.krol@3mdeb.com>2016-05-27 12:04:13 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-19 10:11:13 +0100
commitdcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5 (patch)
tree8ca75267ff1c0fa136680bbe7a87dd8b58e697ee /src/mainboard/pcengines/apu2/OemCustomize.c
parentcff3b095c2fdb7af7b6fb0a1e09c2a66c1ad1c67 (diff)
downloadcoreboot-dcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5.tar.xz
pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/OemCustomize.c')
-rw-r--r--src/mainboard/pcengines/apu2/OemCustomize.c121
1 files changed, 121 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
new file mode 100644
index 0000000000..06a8f3d8af
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+static const PCIe_PORT_DESCRIPTOR PortList [] = {
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x01, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x02, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x03, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x05, 0)
+ }
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+}