pcengines/apu2: add board support

Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.

Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.

memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.

SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872

SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.

Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder

Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 109 insertions, 0 deletions

diff --git a/src/mainboard/pcengines/apu2/acpi/AmdImc.asl b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
new file mode 100644
index 0000000000..d3bb74e31e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+	IMCX,8,
+	IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+	Offset(0x80),
+	MSTI, 8,
+	MITS, 8,
+	MRG0, 8,
+	MRG1, 8,
+	MRG2, 8,
+	MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+	Store(0, Local0)
+	While (LNotEqual(Local0, 0xFA)) {
+		Store(MRG0, Local0)
+		Sleep(10)
+	}
+}
+
+//Init
+Method (ITZE, 0)
+{
+	Store(0, MRG0)
+	Store(0xB5, MRG1)
+	Store(0, MRG2)
+	Store(0x96, MSTI)
+	WACK()
+
+	Store(0, MRG0)
+	Store(0, MRG1)
+	Store(0, MRG2)
+	Store(0x80, MSTI)
+	WACK()
+
+	Or(MRG2, 0x01, Local0)
+
+	Store(0, MRG0)
+	Store(0, MRG1)
+	Store(Local0, MRG2)
+	Store(0x81, MSTI)
+	WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+	Store(0, MRG0)
+	Store(0xB5, MRG1)
+	Store(0, MRG2)
+	Store(0x96, MSTI)
+	WACK()
+
+	Store(0, MRG0)
+	Store(1, MRG1)
+	Store(0, MRG2)
+	Store(0x98, MSTI)
+	WACK()
+
+	Store(0, MRG0)
+	Store(0xB4, MRG1)
+	Store(0, MRG2)
+	Store(0x96, MSTI)
+	WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+	Store(0, MRG0)
+	Store(0xB5, MRG1)
+	Store(0, MRG2)
+	Store(0x96, MSTI)
+	WACK()
+
+	Store(0, MRG0)
+	Store(0, MRG1)
+	Store(0, MRG2)
+	Store(0x80, MSTI)
+	WACK()
+
+	Or(MRG2, 0x01, Local0)
+
+	Store(0, MRG0)
+	Store(0, MRG1)
+	Store(Local0, MRG2)
+	Store(0x81, MSTI)
+	WACK()
+}