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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-03 06:26:27 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-11 22:47:33 +0000 |
| commit | 5ee82832503ab46affbc5f12ce1088046e8ae28c (patch) | |
| tree | 3a608f9a98cb87ac9c9c837467135a32cfcc07ce /src/mainboard/pcengines/apu2/bootblock.c | |
| parent | 1b12b64dab57151d1f04d13d09c1afbf16a7485f (diff) | |
| download | coreboot-5ee82832503ab46affbc5f12ce1088046e8ae28c.tar.xz | |
pcengines/apu2: Switch away from ROMCC_BOOTBLOCK
Add early SuperIO initialization in bootblock to enable early console.
Also, remove some southbridge-specific initialization that has been
moved to southbridge bootblock initialization in previous patch.
The board obtains few additional timestamps: start of bootblock, end
of bootblock, starting to load romstage and finished loading romstage.
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36915
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/pcengines/apu2/bootblock.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/bootblock.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c new file mode 100644 index 0000000000..8318f39287 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_type.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) + +void bootblock_mainboard_early_init(void) +{ + hudson_lpc_port80(); + hudson_clk_output_48Mhz(); + + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} |