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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:58:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-24 09:17:22 +0000 |
| commit | 3cb8abd1b68c9c440e595b15a5216bfd70722c7d (patch) | |
| tree | 18768da970f38dec5d3b7d62cc3d7e3d09fcbf00 /src/mainboard/pcengines/apu2/mainboard.c | |
| parent | 0a490d246c1d2782588f7201290ddf3229382393 (diff) | |
| download | coreboot-3cb8abd1b68c9c440e595b15a5216bfd70722c7d.tar.xz | |
mb/pcengines: Drop unneeded empty lines
Change-Id: Ia1f5c22287be0d228ce1d569f3224d9d63093f3a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/mainboard.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/mainboard.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index aa8c4bcf5e..939f7cbbb6 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -22,7 +22,6 @@ #define PM_RTC_CONTROL 0x56 #define PM_S_STATE_CONTROL 0xBA - /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and |