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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-21 12:32:43 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-26 08:36:05 +0000
commite52738b42889a8bf6b96fe86b87fbdd73947b367 (patch)
treeab3ddcc914b9ab69fdb793ba42e30480d9a8824f /src/mainboard/pcengines/apu2
parente1dced4561ed3b7bff98984c1d51b8e84f004b47 (diff)
downloadcoreboot-e52738b42889a8bf6b96fe86b87fbdd73947b367.tar.xz
AGESA binaryPI boards: Fix some whitespace
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2')
-rw-r--r--src/mainboard/pcengines/apu2/OemCustomize.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index 3c28ac5011..797b75f8be 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -16,11 +16,11 @@
#include <northbridge/amd/pi/agesawrapper.h>
-static const PCIe_PORT_DESCRIPTOR PortList [] = {
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -29,8 +29,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -39,8 +39,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -49,8 +49,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -59,8 +59,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,