diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-02-26 10:11:21 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-08 04:08:00 +0100 |
| commit | 1b183aa6ce78af27c2e42aa51626f76a4b5d5bb0 (patch) | |
| tree | 8148c084ef3cdbc6ed86972694864ef910d6668e /src/mainboard/pcengines/apu2 | |
| parent | 3444a9d716ba52f9bd8fb03870442ab1ce1654cf (diff) | |
| download | coreboot-1b183aa6ce78af27c2e42aa51626f76a4b5d5bb0.tar.xz | |
binaryPI boards: Drop any ACPI S3 support
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2')
| -rw-r--r-- | src/mainboard/pcengines/apu2/mainboard.c | 4 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 36 |
2 files changed, 11 insertions, 29 deletions
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index d2ab63822b..043bc172d0 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/pi/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -183,9 +182,6 @@ static void mainboard_enable(device_t dev) // pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14)); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63cd20..a0d925f0a2 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> #include "gpio_ftns.h" @@ -82,29 +80,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); |