diff options
| author | Paul Menzel <pmenzel@molgen.mpg.de> | 2020-04-24 18:57:04 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-06 09:44:53 +0000 |
| commit | 76d55e5f00a02b69d300ae2d8f8f1851e9ad325a (patch) | |
| tree | e6c1a6dabb4bfb96cd417e2834846986a47d2b5b /src/mainboard/pcengines | |
| parent | b07e262c48eb964617c4413a88c37f0db31805b6 (diff) | |
| download | coreboot-76d55e5f00a02b69d300ae2d8f8f1851e9ad325a.tar.xz | |
amd/pi/hudson boards: Get rid of power button device
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD AGESA Hudson boards
(SOUTHBRIDGE_AMD_PI_AVALON).
The GPE ACPI code seems to originate from commit 806def8c (I missed the
svn add on r3787. These are the additional files., Add AMD dbm690t ACPI
support.), and was copied over.
Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/pcengines')
| -rw-r--r-- | src/mainboard/pcengines/apu2/acpi/gpe.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu2/dsdt.asl | 7 |
2 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl index add15861a2..322e1639ef 100644 --- a/src/mainboard/pcengines/apu2/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl @@ -5,7 +5,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -29,7 +28,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -49,6 +47,5 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 4ee4fd8bfe..e6543b95c3 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -39,13 +39,6 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> |