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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-17 18:08:40 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-02-23 21:36:21 +0100
commitb5a8a13bde537893d1bf150b2d90156e4b855374 (patch)
treeb9ac3ba97d1dc10aa04bf53c26711bd073e3cb75 /src/mainboard/pcengines
parent07354235df303c0c1ea3845f5325993a089b4150 (diff)
downloadcoreboot-b5a8a13bde537893d1bf150b2d90156e4b855374.tar.xz
pcengines/apu1: Fix 0:15.x PCIe root ports
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done to only advertise x1 lane width for PCIe link 0:15.0. Hide functions of PCIe links that have no slots connected. Our PCI infrastructure does not support bridge devices that are set off in devicetree but remain visible in the PCI hardware tree. Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines')
-rw-r--r--src/mainboard/pcengines/apu1/devicetree.cb2
-rw-r--r--src/mainboard/pcengines/apu1/platform_cfg.h4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 7a60885de6..b98f34d4d1 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -83,7 +83,7 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
- register "gpp_configuration" = "0"
+ register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
register "disconnect_pcib" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h
index 08051ec5b7..df2b0ecf30 100644
--- a/src/mainboard/pcengines/apu1/platform_cfg.h
+++ b/src/mainboard/pcengines/apu1/platform_cfg.h
@@ -185,7 +185,7 @@
* GPP_CFGMODE_X2110
* GPP_CFGMODE_X1111
*/
-#define GPP_CFGMODE GPP_CFGMODE_X4000
+#define GPP_CFGMODE GPP_CFGMODE_X1111
/**
* @def NB_SB_GEN2
@@ -206,7 +206,7 @@
* TRUE - ports visible always, even port empty
* FALSE - ports invisible if port empty
*/
-#define SB_GPP_UNHIDE_PORTS TRUE
+#define SB_GPP_UNHIDE_PORTS FALSE
/**
* @def GEC_CONFIG