pcengines/apu1: Fix and clean up devicetree

Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware.

Disable 0:14.1 IDE controller, as it would only be used with SATA ports
4 and 5 that are not populated with connectors in the hardware.

Disable 0:14.2 HD audio, as it is not implemented in the hardware

Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller
are not populated in the hardware.

Fix some alignment and whitespace.

To my knowledge these changes are not included with SAGE release
pcengines.apu_139_osp.tar.gz, but that tarball does not contain
either devicetree.cb or a pre-compiled static.c file so I cannot tell
for sure.

Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8328
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

2 files changed, 33 insertions, 47 deletions

diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index a0a6a35f52..7a60885de6 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -26,29 +26,26 @@ chip northbridge/amd/agesa/family14/root_complex
 	device domain 0 on
 		subsystemid 0x1022 0x1510 inherit
 			chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-#					device pci 18.0 on #  northbridge
-					chip northbridge/amd/agesa/family14 # PCI side of HT root complex
-						device pci 0.0 on end # Root Complex
-						device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456]
-						device pci 4.0 on end # PCIE P2P bridge on-board NIC
-						device pci 5.0 on end # PCIE P2P bridge
-						device pci 6.0 on end # PCIE P2P bridge PCIe slot
-						device pci 7.0 on end # PCIE P2P bridge
-						device pci 8.0 on end # NB/SB Link P2P bridge
-					end # agesa northbridge
+#				device pci 18.0 on #  northbridge
+				chip northbridge/amd/agesa/family14 # PCI side of HT root complex
+					device pci 0.0 on end # Root Complex
+					device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456]
+					device pci 4.0 on end # PCIE P2P bridge on-board NIC
+					device pci 5.0 on end # PCIE P2P bridge
+					device pci 6.0 on end # PCIE P2P bridge PCIe slot
+					device pci 7.0 on end # PCIE P2P bridge
+					device pci 8.0 on end # NB/SB Link P2P bridge
+				end # agesa northbridge
 
-					chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
-						device pci 11.0 on end # SATA
-						device pci 12.0 on end # OHCI USB 0-4
-						device pci 12.1 on end # OHCI USB 0-4
-						device pci 12.2 on end # EHCI USB 0-4
-						device pci 13.0 on end # OHCI USB 5-9
-						device pci 13.1 on end # OHCI USB 5-9
-						device pci 13.2 on end # EHCI USB 5-9
-						device pci 14.0 on # SM
-					end # SM
-					device pci 14.1 on end # IDE	0x439c
-					device pci 14.2 on end # HDA	0x4383
+				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # OHCI USB 0-4
+					device pci 12.2 on end # EHCI USB 0-4
+					device pci 13.0 on end # OHCI USB 5-9
+					device pci 13.2 on end # EHCI USB 5-9
+					device pci 14.0 on end # SMBus
+					device pci 14.1 off end # IDE	0x439c
+					device pci 14.2 off end # HDA	0x4383
 					device pci 14.3 on # LPC		0x439d
 					chip superio/nuvoton/nct5104d
 						register "irq_trigger_type" = "0"
@@ -76,20 +73,20 @@ chip northbridge/amd/agesa/family14/root_complex
 						device pnp 2e.607 off end
 						device pnp 2e.e off end
 					end
-				end #LPC
-				device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-				device pci 14.5 on end # OHCI FS/LS USB
-				#device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-				device pci 15.0 on end # PCIe PortA
-				device pci 15.1 off end # PCIe PortB
-				device pci 15.2 off end # PCIe PortC
-				device pci 15.3 off end # PCIe PortD
-				device pci 16.0 on end # OHCI USB 10-13
-				device pci 16.2 on end # EHCI USB 10-13
-				register "gpp_configuration" = "0"
-				register "disconnect_pcib" = "1"
-				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-			end	#southbridge/amd/cimx/sb800
+					end #LPC
+					device pci 14.4 on end # PCIB 0x4384
+					device pci 14.5 off end # OHCI FS/LS USB
+					#device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
+					device pci 15.0 on end # PCIe PortA
+					device pci 15.1 off end # PCIe PortB
+					device pci 15.2 off end # PCIe PortC
+					device pci 15.3 off end # PCIe PortD
+					device pci 16.0 on end # OHCI USB 10-13
+					device pci 16.2 on end # EHCI USB 10-13
+					register "gpp_configuration" = "0"
+					register "disconnect_pcib" = "1"
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/cimx/sb800
 #			end #  device pci 18.0
 # These seem unnecessary
 			device pci 18.0 on end
diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c
index 18bdb97d30..03fa9f37d6 100644
--- a/src/mainboard/pcengines/apu1/mptable.c
+++ b/src/mainboard/pcengines/apu1/mptable.c
@@ -114,17 +114,6 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
 	PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
 
-	/* PCI slots */
-	device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-		/* PCI_SLOT 0 */
-		PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
-		PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);	/* INTB -> INTF */
-		PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);	/* INTC -> INTG */
-		PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);	/* INTD -> INTH */
-	}
-
 	/* PCIe PortA */
 	PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
 	/* PCIe PortB */