summaryrefslogtreecommitdiff
path: root/src/mainboard/pcengines
diff options
context:
space:
mode:
authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-02-04 15:22:01 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-11 11:40:10 +0000
commit7bfdf5be6397713f776f0a98c2ebcd9340632195 (patch)
treea59e3d398d4c852cf06f288965310a8a417d9b35 /src/mainboard/pcengines
parent8a41f4b71e883ec66be511cb592ee19dfa6708c5 (diff)
downloadcoreboot-7bfdf5be6397713f776f0a98c2ebcd9340632195.tar.xz
src/mainboard/pcengines/apu2/OemCustomize.c: Enable CPB feature
Enable Core Performance Boost feature in automatic mode. Also enable C6 state which is a dependency for proper CPB operation. CPB allows to raise single core frequency from 1000MHz to 1400MHz during high load if other cores idle. The processor has additional boosted P-states when CPB is enabled, but these are hidden from OS. TEST: Higher single-core CPU performance is indicated by increased memory bandwidth as reported by memtest86+. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5e080bfaee06fd13cedf5151d4a598ec212213f2 Reviewed-on: https://review.coreboot.org/c/31229 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/pcengines')
-rw-r--r--src/mainboard/pcengines/apu2/OemCustomize.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index a729860616..700f4c7ca6 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -97,4 +97,6 @@ OemCustomizeInitEarly (
)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->PlatformConfig.CStateMode = CStateModeC6;
+ InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
}