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authorMichał Żygowski <michal.zygowski@3mdeb.com>2020-02-12 13:10:23 +0100
committerMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-25 18:08:56 +0000
commit65f05505a6b7e9e1e9b45c9f6aae34fccd7a7f32 (patch)
treebb48f4b05a0a65f544cce7a0c8ecafc8305d65da /src/mainboard/pcengines
parent48409b82299ed032e151a67b80b2bb257b463172 (diff)
downloadcoreboot-65f05505a6b7e9e1e9b45c9f6aae34fccd7a7f32.tar.xz
superio/nuvoton/nct5104d: add chip config option to reset GPIOs
Define a chip option to explicitly soft reset all enabled GPIOs to default state. TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration using nctgpio module and check whether GPIOs are reset after reboot Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iae4205574800138402cbc95f4948167265a80d15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/pcengines')
-rw-r--r--src/mainboard/pcengines/apu1/devicetree.cb1
-rw-r--r--src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb1
-rw-r--r--src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb1
-rw-r--r--src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb1
4 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 4974cfbfbb..dd851a7133 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -41,6 +41,7 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d
register "irq_trigger_type" = "0"
+ register "reset_gpios" = "1"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
index 3528e86362..672155b049 100644
--- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
@@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
+ register "reset_gpios" = "1"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
index 13643a42c0..d743da6b66 100644
--- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
@@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
+ register "reset_gpios" = "1"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
index f5082d466f..c08e5b24e2 100644
--- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
@@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
+ register "reset_gpios" = "1"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8