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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-04 07:34:13 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-25 20:30:06 +0000
commit5dcf5f666fdf0420409d151c3294e594d3c961c2 (patch)
treee7d49d0a977fac8f44b56d5390166e6084e8e098 /src/mainboard/pcengines
parenta2d9afc5eaa0ddc337d3993ef21720045872fc26 (diff)
downloadcoreboot-5dcf5f666fdf0420409d151c3294e594d3c961c2.tar.xz
pcengines/apu1: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I10b3e53a5e39764e3b199561d07391779804407c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/pcengines')
-rw-r--r--src/mainboard/pcengines/apu1/Kconfig1
-rw-r--r--src/mainboard/pcengines/apu1/OemCustomize.c14
2 files changed, 7 insertions, 8 deletions
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index ecfeebbcb5..66cb65df72 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -18,7 +18,6 @@ if BOARD_PCENGINES_APU1
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select AGESA_LEGACY_WRAPPER
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index 20acb272ac..5be75e9e2e 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -17,7 +17,7 @@
#include "PlatformGnbPcieComplex.h"
#include <string.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
@@ -35,7 +35,7 @@
*
**/
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@@ -124,7 +124,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
- return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@@ -138,7 +137,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
@@ -155,6 +154,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END
};
-const struct OEM_HOOK OemCustomize = {
- .InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}