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| author | Frans Hendriks <fhendriks@eltan.com> | 2021-04-07 11:52:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-14 10:38:50 +0000 |
| commit | 20e04efc3316a02deac325598a02696af01b440d (patch) | |
| tree | e980c98c7ecab4d439ca4ca84ca755e9ffab0e92 /src/mainboard/portwell | |
| parent | c48cf110dd38f6dbbbd146aaec67daa81a56c043 (diff) | |
| download | coreboot-20e04efc3316a02deac325598a02696af01b440d.tar.xz | |
mb/portwell/m107/Kconfig: Remove CACHE_MRC_SETTINGS
The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig.
BUG = N/A
TEST = Build and boot Portwell M107
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I528c582419fb2044f5edfd7a070785489efdf7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/portwell')
| -rw-r--r-- | src/mainboard/portwell/m107/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 3935b38e80..34adfd1b91 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_BRASWELL select PCIEXP_L1_SUB_STATE select HAVE_FSP_BIN - select CACHE_MRC_SETTINGS select DISABLE_HPET select HAVE_SPD_IN_CBFS |