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author | Christian Walter <christian.walter@9elements.com> | 2020-01-09 15:42:42 +0100 |
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committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-06-06 07:44:53 +0000 |
commit | b646e28769f27ee2812925f63fe2f73c67e23c9e (patch) | |
tree | 271b049fe1671304da6425c2f90fff0bffabec90 /src/mainboard/prodrive/hermes/romstage.c | |
parent | b7cf7d36d7cf97b0cce437b9f1577ca39eeb312d (diff) | |
download | coreboot-b646e28769f27ee2812925f63fe2f73c67e23c9e.tar.xz |
mb/prodrive/hermes: Add new mainboard port
This patch adds support for the Prodrive Hermes mainboard.
Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41.
Untested:
* CNVi
* Intel Graphics
Tested:
* CPU Intel Xeon E2288G
* CPU Intel Core i3-9100F
* CPU Intel Core i7 9700KF
* CPU Intel Core i7 9700E
* CPU Intel Core i7 9700F
* CPU Intel Core i5 9600K
* CPU Intel Pentium Gold G5400
* PCIe Link Width x8 on Slot6 by changing PCIe mux
* All four DDR4 slots in different configurations
* USB2.0 HDR1
* USB2.0 HDR2
* USB3.0 HDR
* Slot1
* Slot2
* Slot3
* Slot4
* Slot6
* M2.M NVMEe
* Ethernet PHYs 0-4
* Aspeed BMC PCIe
* Aspeed BMC USB
* Aspeed Graphics init
* USB3 backplane all working
* I801 SMBUS
Not Working:
* Intel HDA
Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/prodrive/hermes/romstage.c')
-rw-r--r-- | src/mainboard/prodrive/hermes/romstage.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c new file mode 100644 index 0000000000..a25c43a743 --- /dev/null +++ b/src/mainboard/prodrive/hermes/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/variants.h> +#include "variants/baseboard/include/eeprom.h" + +static fsp_params parmas_list[] = { + GET_VALUE(RMT), + GET_VALUE(HyperThreading), + GET_VALUE(BootFrequency) +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + memupd->FspmConfig.UserBd = 7; + memupd->FspmTestConfig.SmbusSpdWriteDisable = 0; + memupd->FspmConfig.IedSize = 0x400000; + cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); + + // Overwrite memupd + if (!check_signature(I2C_ADDR_EEPROM)) + return; + + for (size_t i = 0; i < ARRAY_SIZE(parmas_list); i++) { + read_write_config(I2C_ADDR_EEPROM, memupd, EEPROM_OFFSET_FSP_CONFIG + + parmas_list[i].offset, + EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, + parmas_list[i].size); + } +} |