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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 12:54:48 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 12:21:14 +0000
commite16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d (patch)
treea3d4794fb34e6f00d9aee3efc04b1a9173928304 /src/mainboard/prodrive/hermes
parent20245aa622d4224ecd2cdc88438d29f7b5868744 (diff)
downloadcoreboot-e16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d.tar.xz
mb/**/{devicetree,overridetree}.cb: Indent with tabs
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/prodrive/hermes')
-rw-r--r--src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
index 532ab9f3c8..b3649f906e 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -54,13 +54,13 @@ chip soc/intel/cannonlake
register "PcieRpEnable[15]" = "1" # M2 Slot E x1
register "PcieRpEnable[20]" = "1" # Slot 1 x4
# Set MaxPayload to 256 bytes
- register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
- # Enable Latency Tolerance Reporting Mechanism
- register "PcieRpLtrEnable[20]" = "1"
- # Enable Advanced Error Reporting
- register "PcieRpAdvancedErrorReporting[20]" = "1"
- # Disable Aspm
- register "PcieRpAspm[20]" = "AspmDisabled"
+ register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[20]" = "1"
+ # Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[20]" = "1"
+ # Disable Aspm
+ register "PcieRpAspm[20]" = "AspmDisabled"
# Controls the CLKREQ, not the output directly.
# Depends on the CLKREQ to CLK gen mapping below