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author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-03-27 11:35:48 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 21:26:20 +0000 |
commit | 83565dea8638841e522b64e74a4240002bba789d (patch) | |
tree | e985b0f0ad961980be1bfb4e659939c6458c7d32 /src/mainboard/protectli/vault_bsw/mainboard.c | |
parent | 9d422ef3816234195714abae43e3c2d31098e059 (diff) | |
download | coreboot-83565dea8638841e522b64e74a4240002bba789d.tar.xz |
mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/protectli/vault_bsw/mainboard.c')
-rw-r--r-- | src/mainboard/protectli/vault_bsw/mainboard.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/protectli/vault_bsw/mainboard.c b/src/mainboard/protectli/vault_bsw/mainboard.c new file mode 100644 index 0000000000..1fd891918b --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/mainboard.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <arch/mmio.h> +#include <device/device.h> +#include <soc/iomap.h> + +#define BIOS_CONTROL_REG 0xFC +#define BIOS_CONTROL_WPD (1 << 0) + +static void mainboard_enable(struct device *dev) +{ + volatile void *addr = (void *)(SPI_BASE_ADDRESS + BIOS_CONTROL_REG); + + /* Set Bios Write Protect Disable bit to allow saving MRC cache */ + write8(addr, read8(addr) | BIOS_CONTROL_WPD); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; |