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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-03-27 11:35:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 21:26:20 +0000 |
| commit | 83565dea8638841e522b64e74a4240002bba789d (patch) | |
| tree | e985b0f0ad961980be1bfb4e659939c6458c7d32 /src/mainboard/protectli/vault_bsw/ramstage.c | |
| parent | 9d422ef3816234195714abae43e3c2d31098e059 (diff) | |
| download | coreboot-83565dea8638841e522b64e74a4240002bba789d.tar.xz | |
mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/protectli/vault_bsw/ramstage.c')
| -rw-r--r-- | src/mainboard/protectli/vault_bsw/ramstage.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/protectli/vault_bsw/ramstage.c b/src/mainboard/protectli/vault_bsw/ramstage.c new file mode 100644 index 0000000000..6320ca7a67 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + params->PcdTurboMode = 1; +} |