diff options
| author | Youness Alaoui <youness.alaoui@puri.sm> | 2018-03-20 18:32:23 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-06 06:43:00 +0000 |
| commit | 3f42a26b421555dae88bbeae46b7de8835d4e2bd (patch) | |
| tree | 4938f775a4951a42035fbf2da32bbd799ee99795 /src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | |
| parent | cb8f04dc839cd8a339ba3bf55fd4627ff7e78903 (diff) | |
| download | coreboot-3f42a26b421555dae88bbeae46b7de8835d4e2bd.tar.xz | |
purism/librem_skl: Add AC/DC LoadLine to VR Config
The FSP 2.0 needs to set the ac_loadline and dc_loadline for
each VR config. Without it, the Loadline is considered to be
0 mOhm and this causes CPU temp to jump all over the place
whenever the CPU is used.
This is necessary since there are no VR_CONFIG icc mappings for
Skylake SKUs, only KabyLake.
These values were copied from the Google Poppy devicetree.
Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb')
| -rw-r--r-- | src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 40 |
1 files changed, 25 insertions, 15 deletions
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index eff7ecaac4..021f08ad0c 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -31,8 +31,8 @@ chip soc/intel/skylake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # Enable DPTF - register "dptf_enable" = "1" + # Disable DPTF + register "dptf_enable" = "0" # FSP Configuration register "ProbelessTrace" = "0" @@ -81,19 +81,21 @@ chip soc/intel/skylake register "pirqh_routing" = "PCH_IRQ11" # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------------+-------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------+ + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -105,6 +107,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(7), .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, }" register "domain_vr_config[VR_IA_CORE]" = "{ @@ -118,6 +122,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -131,6 +137,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -144,6 +152,8 @@ chip soc/intel/skylake .imon_offset = 0x0, .icc_max = VR_CFG_AMP(35), .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, }" # Enable Root Ports 5 and 9 |