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author | Matt DeVillier <matt.devillier@puri.sm> | 2020-06-26 00:21:39 -0500 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-18 08:48:18 +0000 |
commit | ceb409a2a69075c060736845dc4a444bcb6c212e (patch) | |
tree | 532e1258ea00d4310ad6edf37a00f7520a739af9 /src/mainboard/purism/librem_whl/romstage.c | |
parent | a41b12cd7b8ffa1af1d7b0bc5eae799acd4f86da (diff) | |
download | coreboot-ceb409a2a69075c060736845dc4a444bcb6c212e.tar.xz |
mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
Add new librem_whl baseboard and Librem Mini variant.
Tested with SeaBIOS, Tianocore, and Heads payloads.
All functions working normally except SATA, which is limited
via a FSP UPD to 3Gbps until the correct HSIO PHY settings
can be determined.
https://puri.sm/products/librem-mini/
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/purism/librem_whl/romstage.c')
-rw-r--r-- | src/mainboard/purism/librem_whl/romstage.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c new file mode 100644 index 0000000000..9f8d600950 --- /dev/null +++ b/src/mainboard/purism/librem_whl/romstage.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} |