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authorAngel Pons <th3fanbus@gmail.com>2020-10-23 20:41:09 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-10-30 00:43:51 +0000
commit34672f2bc4e8378d3c24bc026022c36cef261ab1 (patch)
treecc5fb1d711f1c84993f224b8c7c6ef7a738b075a /src/mainboard/purism
parent5e60637ef6ca64bedacbdd5aad1d1a7a85d67c05 (diff)
downloadcoreboot-34672f2bc4e8378d3c24bc026022c36cef261ab1.tar.xz
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/purism')
-rw-r--r--src/mainboard/purism/librem_bdw/devicetree.cb67
-rw-r--r--src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb18
-rw-r--r--src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb18
3 files changed, 55 insertions, 48 deletions
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index b7c6fe58ae..4f34f7d6d4 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -16,10 +16,6 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
- register "gen1_dec" = "0x00000381"
- register "gen2_dec" = "0x000c0081"
-
device cpu_cluster 0 on
device lapic 0 on end
end
@@ -27,33 +23,40 @@ chip soc/intel/broadwell
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
- device pci 13.0 off end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 off end # Serial I/O DMA
- device pci 15.1 off end # I2C0
- device pci 15.2 off end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3 - LAN
- device pci 1c.3 on end # PCIe Port #4 - WiFi
- device pci 1c.4 on end # PCIe Port #5
- device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
- device pci 1d.0 off end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 on end # SMBus
- device pci 1f.6 off end # Thermal
+
+# chip soc/intel/broadwell/pch
+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
+ register "gen1_dec" = "0x00000381"
+ register "gen2_dec" = "0x000c0081"
+
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 off end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3 - LAN
+ device pci 1c.3 on end # PCIe Port #4 - WiFi
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
+ device pci 1d.0 off end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 on end # SMBus
+ device pci 1f.6 off end # Thermal
+# end
end
end
diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
index d3d0ae72d0..237e6979ec 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb
@@ -1,14 +1,16 @@
chip soc/intel/broadwell
- # Port 0 is HDD
- # Port 3 is M.2 NGFF
- register "sata_port_map" = "0x9"
+ device domain 0 on
+# chip soc/intel/broadwell/pch
+ # Port 0 is HDD
+ # Port 3 is M.2 NGFF
+ register "sata_port_map" = "0x9"
- # Port tuning for link stability
- register "sata_port0_gen3_dtle" = "9"
- register "sata_port3_gen3_dtle" = "9"
+ # Port tuning for link stability
+ register "sata_port0_gen3_dtle" = "9"
+ register "sata_port3_gen3_dtle" = "9"
- device domain 0 on
- device pci 1c.2 on end # PCIe Port #3 - LAN
+ device pci 1c.2 on end # PCIe Port #3 - LAN
+# end
end
end
diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
index c0c8d0360f..b9b29cd6ff 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb
@@ -1,14 +1,16 @@
chip soc/intel/broadwell
- # Port 0 is HDD
- # Port 1 is M.2 NGFF
- register "sata_port_map" = "0x3"
+ device domain 0 on
+# chip soc/intel/broadwell/pch
+ # Port 0 is HDD
+ # Port 1 is M.2 NGFF
+ register "sata_port_map" = "0x3"
- # Port tuning for link stability
- register "sata_port0_gen3_dtle" = "7"
- register "sata_port1_gen3_dtle" = "9"
+ # Port tuning for link stability
+ register "sata_port0_gen3_dtle" = "7"
+ register "sata_port1_gen3_dtle" = "9"
- device domain 0 on
- device pci 1d.0 on end # USB2 EHCI
+ device pci 1d.0 on end # USB2 EHCI
+# end
end
end