purism/librem13v2: migrate from FSP 1.1 to 2.0

Migrate the Librem13v2 from using FSP 1.1 to
the public/GitHub FSP 2.0 Skylake/Kabylake release:

- select FSP 2.0 in Kconfig
- adjust romstage/ramstage functions as required
- refactor pei_data functions
- remove VR_RING domain from devicetree (unsupported in FSP 2.0)
- add SataSpeedLimit parameter to work around power-related issue
  when operating at SATA 6.0Gbps speed

TEST: build/boot Librem13v2, observe successful boot, lack of
SATA-related errors in dmesg.

Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 79 insertions, 67 deletions

diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig
index 8522797f6e..5a279551a7 100644
--- a/src/mainboard/purism/librem13v2/Kconfig
+++ b/src/mainboard/purism/librem13v2/Kconfig
@@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOC_INTEL_SKYLAKE
 	# Workaround for EC/KBC IRQ1
 	select SERIRQ_CONTINUOUS_MODE
+	select MAINBOARD_USES_FSP2_0
 
 config IRQ_SLOT_COUNT
 	int
diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index 17c764bb1d..1fc19a5675 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -36,6 +36,7 @@ chip soc/intel/skylake
 	register "SataPortsEnable[2]" = "1"
 	register "SataPortsDevSlp[0]" = "0"
 	register "SataPortsDevSlp[2]" = "0"
+	register "SataSpeedLimit" = "2"
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
@@ -71,20 +72,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-------+-------+-------------+-------+
+	#| Domain/Setting |  SA   |  IA   | GT Unsliced |  GT   |
+	#+----------------+-------+-------+-------------+-------+
+	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A   |
+	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A    |
+	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A    |
+	#| Psi3Enable     | 1     | 1     | 1           | 1     |
+	#| Psi4Enable     | 1     | 1     | 1           | 1     |
+	#| ImonSlope      | 0     | 0     | 0           | 0     |
+	#| ImonOffset     | 0     | 0     | 0           | 0     |
+	#| IccMax         | 7A    | 34A   | 35A         | 35A   |
+	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V |
+	#+----------------+-------+-------+-------------+-------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -111,19 +112,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/purism/librem13v2/pei_data.c b/src/mainboard/purism/librem13v2/pei_data.c
index 730b7307be..0be917d3c7 100644
--- a/src/mainboard/purism/librem13v2/pei_data.c
+++ b/src/mainboard/purism/librem13v2/pei_data.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,8 +19,9 @@
 #include <string.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
+#include "pei_data.h"
 
-void mainboard_fill_pei_data(struct pei_data *pei_data)
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
 {
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
@@ -27,21 +29,37 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
 		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
 		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
 		{ 0, 1, 3, 2, 4, 5, 6, 7 },
 		{ 1, 0, 4, 5, 2, 3, 6, 7 } };
+	memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
 
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
 	/* Rcomp resistor */
 	const u16 RcompResistor[3] = { 121, 81, 100 };
+	memcpy(rcomp_ptr, RcompResistor,
+		 sizeof(RcompResistor));
+}
 
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
 
-	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
-	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
-	memcpy(pei_data->RcompResistor, RcompResistor,
-		 sizeof(RcompResistor));
-	memcpy(pei_data->RcompTarget, RcompTarget,
-		 sizeof(RcompTarget));
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	mainboard_fill_dq_map_data(&pei_data->dq_map);
+	mainboard_fill_dqs_map_data(&pei_data->dqs_map);
+	mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);
 }
diff --git a/src/mainboard/purism/librem13v2/pei_data.h b/src/mainboard/purism/librem13v2/pei_data.h
new file mode 100644
index 0000000000..320d9803d1
--- /dev/null
+++ b/src/mainboard/purism/librem13v2/pei_data.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MAINBOARD_PEI_DATA_H_
+#define _MAINBOARD_PEI_DATA_H_
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+
+#endif
diff --git a/src/mainboard/purism/librem13v2/ramstage.c b/src/mainboard/purism/librem13v2/ramstage.c
index d22e145357..94f8071340 100644
--- a/src/mainboard/purism/librem13v2/ramstage.c
+++ b/src/mainboard/purism/librem13v2/ramstage.c
@@ -17,7 +17,7 @@
 #include <soc/ramstage.h>
 #include "gpio.h"
 
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {
 	/* Configure pads prior to SiliconInit() in case there's any
 	 * dependencies during hardware initialization. */
diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c
index fc940e1a67..48db885075 100644
--- a/src/mainboard/purism/librem13v2/romstage.c
+++ b/src/mainboard/purism/librem13v2/romstage.c
@@ -4,6 +4,7 @@
  * Copyright (C) 2007-2010 coresystems GmbH
  * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,49 +18,29 @@
 
 #include <string.h>
 #include <assert.h>
-#include <arch/acpi.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
 #include <soc/romstage.h>
 #include <spd_bin.h>
+#include "pei_data.h"
 
-void mainboard_romstage_entry(struct romstage_params *params)
-{
-	/* Fill out PEI DATA */
-	mainboard_fill_pei_data(params->pei_data);
-	/* Initliaze memory */
-	romstage_common(params);
-}
-
-void mainboard_memory_init_params(struct romstage_params *params,
-	MEMORY_INIT_UPD *memory_params)
+void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	FSP_M_CONFIG *mem_cfg;
 	struct spd_block blk = {
 		.addr_map = { 0x50 },
 	};
 
+	mem_cfg = &mupd->FspmConfig;
+
 	get_spd_smbus(&blk);
 	dump_spd_info(&blk);
 	assert(blk.spd_array[0][0] != 0);
 
-	memory_params->MemorySpdDataLen = blk.len;
-	memory_params->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
-	memory_params->MemorySpdPtr01 = 0;
-	memory_params->MemorySpdPtr10 = 0;
-	memory_params->MemorySpdPtr11 = 0;
-
-	memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
-		sizeof(params->pei_data->dq_map[0]));
-	memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
-		sizeof(params->pei_data->dq_map[1]));
-	memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
-		sizeof(params->pei_data->dqs_map[0]));
-	memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
-		sizeof(params->pei_data->dqs_map[1]));
-	memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
-		sizeof(params->pei_data->RcompResistor));
-	memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
-		sizeof(params->pei_data->RcompTarget));
-	memory_params->DqPinsInterleaved = TRUE;
+	mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+	mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
 
+	mem_cfg->DqPinsInterleaved = TRUE;
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
 }