diff options
| author | Nico Huber <nico.huber@secunet.com> | 2019-10-02 16:02:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-08-23 09:57:02 +0000 |
| commit | 119ace0908b66b718c4b581423309648b10e4bf7 (patch) | |
| tree | b9ed4510a9081065c35af99a06446a74b3db82c1 /src/mainboard/purism | |
| parent | 2b9035ed6e51fe835b85dd626e655e1d3901e7ea (diff) | |
| download | coreboot-119ace0908b66b718c4b581423309648b10e4bf7.tar.xz | |
soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.
Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/purism')
| -rw-r--r-- | src/mainboard/purism/librem_whl/devicetree.cb | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb index c122bb8982..fc3f418c6f 100644 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -293,12 +293,18 @@ chip soc/intel/cannonlake device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on end # PCI Express Port 8 (WLAN) + device pci 1c.7 on # PCI Express Port 8 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" + end device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 (LAN) + device pci 1d.1 on # PCI Express Port 10 (LAN) + register "PcieRpSlotImplemented[9]" = "1" + end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (NVMe) + device pci 1d.4 on # PCI Express Port 13 (NVMe) + register "PcieRpSlotImplemented[12]" = "1" + end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 |