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authorYouness Alaoui <youness.alaoui@puri.sm>2017-05-25 14:48:18 -0500
committerMartin Roth <martinroth@google.com>2017-06-09 17:02:21 +0200
commit0e977fca9ccaa2fe7c044f71a513b56799d93383 (patch)
tree7b516e91d4db9edb7f9efdb5931facd4f24d4675 /src/mainboard/purism
parent34a30a648f7689dbb587bf316f1e0e761b408d1e (diff)
downloadcoreboot-0e977fca9ccaa2fe7c044f71a513b56799d93383.tar.xz
purism/librem13v2: Add memory init code
Adding code to setup the spd information from sodimm. Adapted from intel/kblrvp. Change-Id: I0403f999dac1bdef0e9e1abe7c9c62407e223bb1 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/purism')
-rw-r--r--src/mainboard/purism/librem13v2/Kconfig9
-rw-r--r--src/mainboard/purism/librem13v2/romstage.c34
2 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig
index 2b3c0642ea..4de48a98af 100644
--- a/src/mainboard/purism/librem13v2/Kconfig
+++ b/src/mainboard/purism/librem13v2/Kconfig
@@ -46,4 +46,13 @@ config VGA_BIOS_ID
string
default "8086,1916"
+config DIMM_MAX
+ int
+ default 1
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+
endif
diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c
index da1c4c3743..bd5520a7c4 100644
--- a/src/mainboard/purism/librem13v2/romstage.c
+++ b/src/mainboard/purism/librem13v2/romstage.c
@@ -16,10 +16,12 @@
*/
#include <string.h>
+#include <assert.h>
#include <arch/acpi.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
+#include <spd_bin.h>
void mainboard_romstage_entry(struct romstage_params *params)
{
@@ -28,3 +30,35 @@ void mainboard_romstage_entry(struct romstage_params *params)
/* Initliaze memory */
romstage_common(params);
}
+
+void mainboard_memory_init_params(struct romstage_params *params,
+ MEMORY_INIT_UPD *memory_params)
+{
+ struct spd_block blk = {
+ .addr_map = { 0xa0 },
+ };
+
+ memory_params->DqPinsInterleaved = 1;
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+ memory_params->MemorySpdDataLen = blk.len;
+ assert(blk.spd_array[0][0] != 0);
+ memory_params->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ memory_params->MemorySpdPtr01 = 0;
+ memory_params->MemorySpdPtr10 = 0;
+ memory_params->MemorySpdPtr11 = 0;
+
+ memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
+ sizeof(params->pei_data->dq_map[0]));
+ memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
+ sizeof(params->pei_data->dq_map[1]));
+ memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
+ sizeof(params->pei_data->dqs_map[0]));
+ memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
+ sizeof(params->pei_data->dqs_map[1]));
+ memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
+ sizeof(params->pei_data->RcompResistor));
+ memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
+ sizeof(params->pei_data->RcompTarget));
+
+}