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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-15 00:27:59 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-26 06:49:40 +0000 |
| commit | d5a45470c816bc8a8bdc43951c9e4c4a592b55d3 (patch) | |
| tree | be365703931ffba49c9ed2abbe9d6af85cc1759b /src/mainboard/razer/blade_stealth_kbl/devicetree.cb | |
| parent | 6267cc523b4a6f716060214d06a8226412a65837 (diff) | |
| download | coreboot-d5a45470c816bc8a8bdc43951c9e4c4a592b55d3.tar.xz | |
soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead
of relying on the devicetree option `speed_shift_enable`, that is going
to be dropped.
Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F
Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/razer/blade_stealth_kbl/devicetree.cb')
0 files changed, 0 insertions, 0 deletions