Add Razer Blade Stealth (2016) H2U

The Razer Blade Stealth H2U is a KabyLake System using:
- Intel KBL 7500U
- ITE8528E SuperIO
- Intel 600P Series NVMe SSD
- Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB)
  of soldered memory in dualchannel mode
- (Optional) Touchscreen
- HDMI 2.0a via DP-1: Paradetech PS175
- AlpineRidge Thunderbolt 3 controller
- TPS65982 USB-PD power switch / multiplexer

Even though it has a 16MB chip equipped (W25Q128.V) only the first 8MB
are used and mapped via IFD. The rest is left empty (0xFF). The flash is
not secured in any way and can be read via flashrom. It should be the
source for this port's IFD and ME blobs.

Working:
- USB-A Ports left and right
- Speakers
- Touchscreen (USB)
- Onboard Keyboard in Linux
- NVMe SSD
- SeaBIOS, Tianocore and Grub Payloads
- Webcam
- Powersaving Modes
- Battery state and LID switch, sometimes slow to update.
- Touchpad (I2C-HID)
- Headphones

Not part of this commit:
- Thunderbolt / USB-C (Requires advanced EC signaling)
- Full HDMI support (Currently requires plugged connection at boot)

Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

1 files changed, 277 insertions, 0 deletions

diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
new file mode 100644
index 0000000000..deb98690f8
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -0,0 +1,277 @@
+chip soc/intel/skylake
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+	register "eist_enable" = "1"
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "GPP_C"
+	register "gpe0_dw1" = "GPP_D"
+	register "gpe0_dw2" = "GPP_E"
+
+	register "gen1_dec" = "0x000c0081"
+	register "gen2_dec" = "0x000c0681"
+	register "gen3_dec" = "0x000c1641"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+	# FSP Configuration
+	register "ProbelessTrace" = "0"
+	register "EnableLan" = "0"
+	register "EnableSata" = "0"
+	register "SataSalpSupport" = "0"
+	register "SataMode" = "0"
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "0"
+	register "SataPortsEnable[2]" = "0"
+	register "EnableAzalia" = "1"
+	register "DspEnable" = "0"
+	register "IoBufferOwnership" = "0"
+	register "EnableTraceHub" = "0"
+	register "SsicPortEnable" = "0"
+	register "SmbusEnable" = "1"
+	register "Cio2Enable" = "0"
+	register "ScsEmmcEnabled" = "0"
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsSdCardEnabled" = "0"
+	register "PttSwitch" = "0"
+	register "SkipExtGfxScan" = "1"
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "1"
+	register "SaGv" = "SaGv_Enabled"
+	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
+	register "PmConfigSlpS4MinAssert" = "1"		# 1s
+	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
+	register "PmConfigSlpAMinAssert" = "3"		# 2s
+	register "PmTimerDisabled" = "0"
+
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 6A        | 64A       | 31A         | 31A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
+	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(4),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 0,
+		.psi4enable = 0,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = VR_CFG_AMP(6),
+		.voltage_limit = 1520,
+		.ac_loadline = 1030,
+		.dc_loadline = 1030,
+	}"
+
+	register "domain_vr_config[VR_IA_CORE]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 0,
+		.psi4enable = 0,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = VR_CFG_AMP(64),
+		.voltage_limit = 1520,
+		.ac_loadline = 240,
+		.dc_loadline = 240,
+	}"
+
+	register "domain_vr_config[VR_GT_UNSLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 0,
+		.psi4enable = 0,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = VR_CFG_AMP(31),
+		.voltage_limit = 1520,
+		.ac_loadline = 310,
+		.dc_loadline = 310,
+	}"
+
+	register "domain_vr_config[VR_GT_SLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 0,
+		.psi4enable = 0,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = VR_CFG_AMP(31),
+		.voltage_limit = 1520,
+		.ac_loadline = 310,
+		.dc_loadline = 310,
+	}"
+
+	# Enable Root Ports 3, 5 and 9
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[8]" = "1"
+
+	register "PcieRpLtrEnable[2]" = "1"
+	register "PcieRpLtrEnable[4]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+
+	register "PcieRpHotPlug[4]" = "1"
+
+	# USB
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"		# Type-A Port (right)
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"		# Type-A Port (left)
+
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# TODO Unknown. Maybe USBC?
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"		# TODO Unknown. Maybe USBC?
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC1)"		# TODO Unknown. Maybe USBC?
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# TODO Unknown. Maybe USBC?
+
+	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)"	# Camera
+	register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)"	# Keyboard
+	register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)"	# Touchscreen
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A Port (left)
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A Port (right)
+
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"	# TODO Unknown. Maybe USBC?
+
+	# PL1 override 25W
+	register "tdp_pl1_override" = "25"
+
+	# PL2 override 44W
+	register "tdp_pl2_override" = "44"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
+	}"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 off end # Thermal Subsystem
+		device pci 08.0 off end # Gaussian Mixture Model
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Thermal Subsystem
+		device pci 15.0 on  end # I2C Controller #0
+		device pci 15.1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x2c on end
+			end
+		end # I2C Controller #1
+		device pci 15.2 off end # I2C Controller #2
+		device pci 15.3 off end # I2C Controller #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 off end # SATA
+		device pci 19.0 on  end # I2C Controller #4
+		device pci 19.1 off end # I2C Controller #5
+		device pci 19.2 off end # UART #2
+		device pci 1c.0 on  end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1e.0 on  end # Serial IO UART0
+		device pci 1f.0 on # LPC
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+			chip superio/ite/it8528e
+				device pnp 6e.1 off end
+				device pnp 6e.2 off end
+				device pnp 6e.3 off end
+				device pnp 6e.4 off end
+				device pnp 6e.5 off end
+				device pnp 6e.6 off end
+				device pnp 6e.a off end
+				device pnp 6e.f off end
+				device pnp 6e.10 off end
+				device pnp 6e.11 off end
+				device pnp 6e.12 off end
+				device pnp 6e.13 off end
+				device pnp 6e.14 off end
+				device pnp 6e.17 off end
+				device pnp 6e.18 off end
+				device pnp 6e.19 off end
+			end	#superio/ite/it8528e
+		end # LPC Bridge
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end