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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-04 21:33:39 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-06 01:51:42 +0100
commit77757c22b9eede92234d07d65a23fdf4b970c8cf (patch)
tree29949ed8cfac9c5c9b2cf4c8071c74690411d32d /src/mainboard/rca/rm4100
parentd76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 (diff)
downloadcoreboot-77757c22b9eede92234d07d65a23fdf4b970c8cf.tar.xz
mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/rca/rm4100')
-rw-r--r--src/mainboard/rca/rm4100/romstage.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index 500416ae1e..9da69b5338 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -27,11 +27,11 @@
#include <console/console.h>
#include <lib.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include "northbridge/intel/i82830/raminit.h"
+#include <northbridge/intel/i82830/raminit.h>
#include "northbridge/intel/i82830/memory_initialized.c"
-#include "southbridge/intel/i82801dx/i82801dx.h"
+#include <southbridge/intel/i82801dx/i82801dx.h>
#include "southbridge/intel/i82801dx/reset.c"
-#include "cpu/x86/bist.h"
+#include <cpu/x86/bist.h>
#include "spd_table.h"
#include "gpio.c"
#include "southbridge/intel/i82801dx/tco_timer.c"