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authorStefan Reinauer <stepan@coresystems.de>2010-04-14 07:47:07 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-14 07:47:07 +0000
commitccdd20a539f81591df3ca5d89e2b74663865e0b1 (patch)
tree81c5d30eb7807baabea8a78045ac9878c7dd357b /src/mainboard/rca
parent1abf46c74ed34eb394921d2f72817c728e3bb9ee (diff)
downloadcoreboot-ccdd20a539f81591df3ca5d89e2b74663865e0b1.tar.xz
move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.
this patch also slightly changes it so we have a single cache_as_ram.inc which requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or worse, a lot of cruft hacked right into romstage.c like on tyan s2735) Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/rca')
-rw-r--r--src/mainboard/rca/rm4100/romstage.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index c93cec6b37..5830af0b40 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -97,9 +97,7 @@ static void mb_early_setup(void)
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
}
-#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
-
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
if (bist == 0) {
if (memory_initialized()) {