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authorPatrick Georgi <patrick.georgi@secunet.com>2011-01-27 07:39:38 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2011-01-27 07:39:38 +0000
commita470019b7a19e164b5dc93b1d541dc4158edbeda (patch)
tree48156b3fb7f795cbe3241f787b642460aa03a29d /src/mainboard/roda/rk886ex/devicetree.cb
parenta5c949eff288af3eb4caffec57a3724c497150de (diff)
downloadcoreboot-a470019b7a19e164b5dc93b1d541dc4158edbeda.tar.xz
Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the variable reset, it's not. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/roda/rk886ex/devicetree.cb')
-rw-r--r--src/mainboard/roda/rk886ex/devicetree.cb4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index 8762955b60..a139e25966 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -83,7 +83,9 @@ chip northbridge/intel/i945
#device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47n227
- device pnp 2e.1 off # Parallel port
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 5
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8