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authorArthur Heymans <arthur@aheymans.xyz>2019-01-07 15:30:21 +0100
committerNico Huber <nico.h@gmx.de>2019-01-08 14:27:43 +0000
commitd25109905aa46fce557d2905a43c347ca5be1aa0 (patch)
treed4eca1b950e3f394a3b58a6a02bcd26a25b1be18 /src/mainboard/roda/rk886ex/devicetree.cb
parent458297c8ba237808a3cdf698f9c7c561b13c0b6c (diff)
downloadcoreboot-d25109905aa46fce557d2905a43c347ca5be1aa0.tar.xz
mb/{ga-g41m-es2l,d945gclf,rk886ex}: Fix devicetree
The devicetree was synced incorrectly with respect to the function disable register set in romstage. Change-Id: I189c5fdc433b5577ae008abf42878cdc6e3f2d52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30711 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/roda/rk886ex/devicetree.cb')
-rw-r--r--src/mainboard/roda/rk886ex/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index e3bcc5b8a0..ec4276619e 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -63,7 +63,7 @@ chip northbridge/intel/i945
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio
+ device pci 1b.0 off end # High Definition Audio
device pci 1c.0 on end # PCIe port 1
device pci 1c.1 off end # PCIe port 2
device pci 1c.2 off end # PCIe port 3
@@ -84,7 +84,7 @@ chip northbridge/intel/i945
device pci 3.3 off end # smartcard
end
end # PCI bridge
- device pci 1e.2 off end # AC'97 Audio
+ device pci 1e.2 on end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47n227