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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-22 11:50:52 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-22 11:50:52 +0000 |
| commit | 53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72 (patch) | |
| tree | 1434912235e0ea29b20b4276ffbfce4f45e12dd5 /src/mainboard/roda/rk886ex/romstage.c | |
| parent | c02b4fc9db3c3c1e263027382697b566127f66bb (diff) | |
| download | coreboot-53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72.tar.xz | |
drop some unused files and fix warnings on i945 based systems.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/roda/rk886ex/romstage.c')
| -rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 4052c3277a..da196a9d5d 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -79,9 +79,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } + #include "northbridge/intel/i945/raminit.h" #include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/reset_test.c" #include "northbridge/intel/i945/errata.c" #include "northbridge/intel/i945/debug.c" @@ -259,8 +259,6 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include "southbridge/intel/i82801gx/cmos_failover.c" - static void init_artec_dongle(void) { // Enable 4MB decoding @@ -277,6 +275,7 @@ static void init_artec_dongle(void) // __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c" +#include "cpu/intel/model_6ex/cache_as_ram_disable.c" void real_main(unsigned long bist) { @@ -391,7 +390,7 @@ void real_main(unsigned long bist) * day. */ if (resume_backup_memory) - memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); @@ -399,4 +398,3 @@ void real_main(unsigned long bist) #endif } -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" |