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author | Patrick Georgi <patrick.georgi@secunet.com> | 2011-01-27 07:39:38 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2011-01-27 07:39:38 +0000 |
commit | a470019b7a19e164b5dc93b1d541dc4158edbeda (patch) | |
tree | 48156b3fb7f795cbe3241f787b642460aa03a29d /src/mainboard/roda/rk886ex/romstage.c | |
parent | a5c949eff288af3eb4caffec57a3724c497150de (diff) | |
download | coreboot-a470019b7a19e164b5dc93b1d541dc4158edbeda.tar.xz |
Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS,
with the variable reset, it's not.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/roda/rk886ex/romstage.c')
-rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index cf36c7cda7..fce53da167 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -36,6 +36,7 @@ #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#include "option_table.h" void setup_ich7_gpios(void) { @@ -68,12 +69,16 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { + int lpt_en = 0; + if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); // Enable 0x02e0 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); |