roda/rk9: New mainboard

Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory.
http://roda-computer.com/products/notebooks/rk9/

Tested with various Linux versions, known to work:
- 2x4GB RAM
- IGD
- HD Audio
- UHCI, EHCI
- AHCI
- NIC
- PCI
- PS/2 keyboard
- serial console
- ACPI lid switch
- ACPI battery/AC events
- power off, reboot

Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1691
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

10 files changed, 1526 insertions, 0 deletions

diff --git a/src/mainboard/roda/rk9/acpi/battery.asl b/src/mainboard/roda/rk9/acpi/battery.asl
new file mode 100644
index 0000000000..3eb9b14e49
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/battery.asl
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name(\CBA1, 0x60)
+Name(\CBA2, 0x60)
+
+/* ACPI doesn't care if capacity is given in mWh or mAh,
+   but it has to be consistent */
+
+Device (BAT1)
+{
+	Name(_HID, EisaId("PNP0C0A"))
+	Name(_UID, 1)
+
+	Name(_PCL, Package(){ _SB })
+	Name(PSTA, 0x1f)
+
+	/* battery information */
+	Name(PBIF, Package() {
+		0x01,	// power unit
+		0x01,	// design capacity (mWh/mAh), updated by UPBI
+		0x01,	// last full charge capacity (mWh/mAh), updated by UPBI
+		0x01,	// battery technology: "rechargeable"
+		0x01,	// design voltage (mV), updated by UPBI
+		0x0294,	// design capacity of warning (mWh/mAh)
+		0x014a, // design capacity of low (mWh/mAh)
+		0x42,	// battery capacity granularity between low and warning
+		0x42,	// battery capacity granularity between warning and full
+		"BAT1",	// Name
+		"001 ",	// Number
+		"LION",	// Type
+		"JSE"	// Vendor
+	})
+	/* battery status */
+	/* dummy values, filled in by UPBS */
+	Name(PBST, Package() {
+		0x00,	// battery state
+			// bit0: discharging
+			// bit1: charging
+			// bit2: critical energy state
+		0x01,	// battery present rate (mW/mA)
+		0x01,	// remaining capacity (mW/mA)
+		0x01	// battery present voltage (mV)
+	})
+
+	/* Status */
+	Method(_STA, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			If(\_SB.PCI0.LPCB.EC0.B1PR) {
+				If(\_SB.PCI0.LPCB.EC0.B1CH) {
+					Return(0x1f)
+				}
+			}
+		}
+		Return(0x0f)
+	}
+
+	/* Battery Info */
+	Method(_BIF, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			Store (\_SB.PCI0.LPCB.EC0.B1DW, Index(PBIF, 1))
+			Store (\_SB.PCI0.LPCB.EC0.B1FW, Index(PBIF, 2))
+			Store (\_SB.PCI0.LPCB.EC0.B1DV, Index(PBIF, 4))
+		}
+
+		Return(PBIF)
+	}
+
+	/* Battery Status */
+	Method(_BST, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			Store (\_SB.PCI0.LPCB.EC0.B1PW, Local0)
+			If (LGreaterEqual (Local0, 0x8000)) {
+				Subtract (0x10000, Local0, Local0)
+			}
+			Store (Local0, Index(PBST, 1))
+			Store (\_SB.PCI0.LPCB.EC0.B1PV, Index(PBST, 3))
+
+			Store (\_SB.PCI0.LPCB.EC0.B1RW, Index(PBST, 2))
+
+			If (\_SB.PCI0.LPCB.EC0.ACCH) {
+				If (\_SB.PCI0.LPCB.EC0.B1CH) {
+					If (\_SB.PCI0.LPCB.EC0.B1CG) {
+						Store (2, Index(PBST, 0))
+					}
+				}
+			} Else {
+				If (\_SB.PCI0.LPCB.EC0.B1LO) {
+					Store (5, Index(PBST, 0))
+				} Else {
+					Store (1, Index(PBST, 0))
+				}
+			}
+		}
+
+		Return(PBST)
+	}
+
+}
+
+Device (BAT2)
+{
+	Name(_HID, EisaId("PNP0C0A"))
+	Name(_UID, 2)
+
+	Name(_PCL, Package(){ _SB })
+	Name(PSTA, 0x1f)
+
+	/* battery information */
+	Name(PBIF, Package() {
+		0x01,	// power unit
+		0x01,	// design capacity (mWh/mAh), updated by UPBI
+		0x01,	// last full charge capacity (mWh/mAh), updated by UPBI
+		0x01,	// battery technology: "rechargeable"
+		0x01,	// design voltage (mV), updated by UPBI
+		0x0294,	// design capacity of warning (mWh/mAh)
+		0x014a, // design capacity of low (mWh/mAh)
+		0x42,	// battery capacity granularity between low and warning
+		0x42,	// battery capacity granularity between warning and full
+		"BAT1",	// Name
+		"002 ",	// Number
+		"LION",	// Type
+		"JSE"	// Vendor
+	})
+	/* battery status */
+	/* dummy values, filled in by UPBS */
+	Name(PBST, Package() {
+		0x00,	// battery state
+			// bit0: discharging
+			// bit1: charging
+			// bit2: critical energy state
+		0x01,	// battery present rate (mW/mA)
+		0x01,	// remaining capacity (mW/mA)
+		0x01	// battery present voltage (mV)
+	})
+
+	/* Status */
+	Method(_STA, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			If(\_SB.PCI0.LPCB.EC0.B2PR) {
+				If(\_SB.PCI0.LPCB.EC0.B2CH) {
+					Return(0x1f)
+				}
+			}
+		}
+		Return(0x0f)
+	}
+
+	/* Battery Info */
+	Method(_BIF, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			Store (\_SB.PCI0.LPCB.EC0.B2DW, Index(PBIF, 1))
+			Store (\_SB.PCI0.LPCB.EC0.B2FW, Index(PBIF, 2))
+			Store (\_SB.PCI0.LPCB.EC0.B2DV, Index(PBIF, 4))
+		}
+
+		Return(PBIF)
+	}
+
+	/* Battery Status */
+	Method(_BST, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			Store (\_SB.PCI0.LPCB.EC0.B2PW, Local0)
+			If (LGreaterEqual (Local0, 0x8000)) {
+				Subtract (0x10000, Local0, Local0)
+			}
+			Store (Local0, Index(PBST, 1))
+			Store (\_SB.PCI0.LPCB.EC0.B2PV, Index(PBST, 3))
+
+			Store (\_SB.PCI0.LPCB.EC0.B2RW, Index(PBST, 2))
+
+			If (\_SB.PCI0.LPCB.EC0.ACCH) {
+				If (\_SB.PCI0.LPCB.EC0.B2CH) {
+					If (\_SB.PCI0.LPCB.EC0.B2CG) {
+						Store (2, Index(PBST, 0))
+					}
+				}
+			} Else {
+				If (\_SB.PCI0.LPCB.EC0.B2LO) {
+					Store (5, Index(PBST, 0))
+				} Else {
+					Store (1, Index(PBST, 0))
+				}
+			}
+		}
+
+		Return(PBST)
+	}
+
+}
+
+Device (ADP1)
+{
+	Name (_HID, "ACPI0003")
+	Method (_PSR, 0)
+	{
+		Store (\_SB.PCI0.LPCB.EC0.ACCH, PWRS)
+		Stall (0x02)
+		Return (PWRS)
+	}
+
+	Method (_PCL, 0)
+	{
+		Return (_SB)
+	}
+}
+
diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl
new file mode 100644
index 0000000000..3e6cb98cc2
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/ec.asl
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 1)
+
+	Name (_GPE, 23)	// GPI07 / GPE23 -> Runtime SCI
+	Name (ECON, 0)
+	Name (QEVT, 0)
+
+	OperationRegion(ERAM, EmbeddedControl, 0x00, 0xff)
+	Field (ERAM, ByteAcc, NoLock, Preserve)
+	{
+			Offset(0xb1),
+		CPWR,   1,
+		ACCH,   1, // AC connected (charger present)
+		B1PR,   1, // battery 1 present
+		B2PR,   1, // battery 2 present
+		B1CH,   1, // battery 1 charged
+		B2CH,   1, // battery 2 charged
+			Offset(0xb2),
+		B1CG,   1, // battery 1 charging
+		B2CG,   1, // battery 2 charging
+		B1LO,   1, // battery 1 low
+		B2LO,   1, // battery 2 low
+			Offset(0xb3),
+		B1DW,  16, // battery 1 design capacity
+		B1FW,  16, // battery 1 last full charge capacity
+		B1DV,  16, // battery 1 design voltage
+		B1PW,  16, // battery 1 present capacity
+			Offset(0xbd),
+		B1PV,  16, // battery 1 present voltage
+			Offset(0xc1),
+		B2DW,  16, // battery 2 design capacity
+		B2FW,  16, // battery 2 last full charge capacity
+		B2DV,  16, // battery 2 design voltage
+		B2PW,  16, // battery 2 present capacity
+			Offset(0xcb),
+		B2PV,  16, // battery 2 present voltage
+			Offset(0xcf),
+		FDDI,   1, // floppy on lpt indicator?
+		LIDC,   1, // LID switch
+			Offset(0xd0),
+		TCPU,   8, // T_CPU in deg Celcius
+			Offset(0xd6),
+		/* exact purpose of these three is guessed,
+		   but it's something about cooling */
+		ALRL,   1, // active cooling low limit
+		ALRH,   1, // active cooling high limit
+		ALRC,   1, // active cooling clear
+			Offset(0xe8),
+		B1RW,  16, // battery 1 remaining capacity
+		B2RW,  16, // battery 2 remaining capacity
+	}
+
+	Method (_CRS, 0)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 1, 1)
+			IO (Decode16, 0x66, 0x66, 1, 1)
+		})
+
+		Return (ECMD)
+	}
+
+	Method (_REG, 2)
+	{
+		// This method is needed by Windows XP/2000 for
+		// EC initialization before a driver is loaded
+
+		If (LEqual(Arg0, 0x03)) {
+			Store (Arg1, ECON)
+		}
+	}
+
+	// EC Query methods
+
+	Method (_Q11, 0)
+	{
+		Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug)
+		Notify(SLPB, 0x80)
+	}
+
+	Method (_Q30, 0)
+	{
+		Store("_Q30: AC In", Debug)
+		Notify(ADP1, 0x80)	// Tell the Power Adapter
+		PNOT()			// and the CPU and Battery
+	}
+
+	Method (_Q31, 0)
+	{
+		Store("_Q31: AC Out", Debug)
+		Notify(ADP1, 0x80)	// Tell the Power Adapter
+		PNOT()			// and the CPU and Battery
+	}
+
+	Method (_Q32, 0)
+	{
+		Store("_Q32: Bat1 In", Debug)
+		Notify(BAT1, 0x81)
+	}
+
+	Method (_Q33, 0)
+	{
+		Store("_Q33: Bat1 Out", Debug)
+		Notify(BAT1, 0x81)
+	}
+
+	Method (_Q34, 0)
+	{
+		Store("_Q34: Bat2 In", Debug)
+		Notify(BAT2, 0x81)
+	}
+
+	Method (_Q35, 0)
+	{
+		Store("_Q35: Bat2 Out", Debug)
+		Notify(BAT2, 0x81)
+	}
+
+	Method (_Q36, 0)
+	{
+		Store("_Q36: Bat1 Low Power", Debug)
+		Notify(BAT1, 0x80)
+	}
+
+	Method (_Q37, 0)
+	{
+		Store("_Q37: Bat1 Full Charge", Debug)
+		Notify(BAT1, 0x80)
+	}
+
+	Method (_Q38, 0)
+	{
+		Store("_Q38: Bat2 Low Power", Debug)
+		Notify(BAT2, 0x80)
+	}
+
+	Method (_Q39, 0)
+	{
+		Store("_Q39: Bat2 Full Charge", Debug)
+		Notify(BAT2, 0x80)
+	}
+
+	Method (_Q40, 0)
+	{
+		Store("_Q40: LID Open/Close", Debug)
+		Notify(LID0, 0x80)
+	}
+
+	Method (_Q41, 0)
+	{
+		Store("_Q41: Floppy on Parallel Port: Call the Museum!", Debug)
+	}
+
+	Method (_Q50, 0)
+	{
+		Store("_Q50: Processor is hot", Debug)
+		Notify(\_TZ.THRM, 0x80)
+	}
+
+	Method (_Q51, 0)
+	{
+		Store("_Q51: Processor is boiling", Debug)
+		Notify(\_TZ.THRM, 0x80)
+	}
+
+	Method (_Q52, 0)
+	{
+		Store("_Q52: Processor is burning", Debug)
+		Notify(\_TZ.THRM, 0x80)
+	}
+
+}
diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl
new file mode 100644
index 0000000000..83c7762601
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * gm45
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, 0, 16 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// USB and EHCI			0:1a.x
+			Package() { 0x001affff, 0, 0, 16 },
+			Package() { 0x001affff, 1, 0, 17 },
+			Package() { 0x001affff, 2, 0, 18 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 16 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, 0, 16 },
+			Package() { 0x001dffff, 1, 0, 17 },
+			Package() { 0x001dffff, 2, 0, 18 },
+			// FIXME
+			// CardBus/IEEE1394		0:1e.2, 0:1e.3
+			// Package() { 0x001effff, 0, 0, 22 },
+			// Package() { 0x001effff, 1, 0, 20 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, 0, 16 },
+			Package() { 0x001fffff, 1, 0, 17 },
+			Package() { 0x001fffff, 2, 0, 18 }
+		})
+	} Else {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// USB and EHCI			0:1a.x
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			// FIXME
+			// CardBus/IEEE1394		0:1e.2, 0:1e.3
+			// Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
+		})
+	}
+}
+
diff --git a/src/mainboard/roda/rk9/acpi/gpe.asl b/src/mainboard/roda/rk9/acpi/gpe.asl
new file mode 100644
index 0000000000..58540063da
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/gpe.asl
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (_GPE)
+{
+	/* The event numbers correspond to the bit numbers in the
+	 * GPE0_EN register PMBASE + 0x28.
+	 */
+	/* IMO we don't need empty Methods here. If we don't specify
+	   one and don't set the GPE0_EN bit Linux won't neither enable
+	   it. - Nico */
+
+	// Thermal Event - original BIOS doesn't have it
+	Method (_L00, 0)
+	{
+		/* FIXME: We should enable throttling here. */
+	}
+
+	// Hot Plug
+	Method (_L01, 0)
+	{
+
+	}
+
+	// USB1
+	Method (_L03, 0)
+	{
+
+	}
+
+	// USB2
+	Method (_L04, 0)
+	{
+
+	}
+
+	// USB5
+	Method (_L05, 0)
+	{
+
+	}
+
+	// _L06 TCOSCI
+
+	// SMBus Wake Status
+	Method (_L07, 0)
+	{
+
+	}
+
+	// COM1/COM2 (RI)
+	Method (_L08, 0)
+	{
+
+	}
+
+	// PCIe
+	Method (_L09, 0)
+	{
+
+	}
+
+	// _L0A BatLow / Quick Resume
+
+	// PME
+	Method (_L0B, 0)
+	{
+
+	}
+
+	// USB3
+	Method (_L0C, 0)
+	{
+
+	}
+
+	// PME B0
+	Method (_L0D, 0)
+	{
+
+	}
+
+	// USB4
+	Method (_L0E, 0)
+	{
+
+	}
+
+	// _L10 - _L1f: GPIn
+
+	// GPI8
+	Method (_L18, 0)
+	{
+
+	}
+
+	// USB6
+	Method (_L20, 0)
+	{
+
+	}
+}
diff --git a/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl
new file mode 100644
index 0000000000..325f13cc2e
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH9
+ */
+
+/* TODO: which slots are actually relevant? */
+If (PICM) {
+	Return (Package() {
+		// PCI Slot 1 routes ABCD
+		Package() { 0x0000ffff, 0, 0, 16},
+		Package() { 0x0000ffff, 1, 0, 17},
+		Package() { 0x0000ffff, 2, 0, 18},
+		Package() { 0x0000ffff, 3, 0, 19},
+
+		// PCI Slot 2 routes BCDA
+		Package() { 0x0001ffff, 0, 0, 17},
+		Package() { 0x0001ffff, 1, 0, 18},
+		Package() { 0x0001ffff, 2, 0, 19},
+		Package() { 0x0001ffff, 3, 0, 16},
+
+		// PCI Slot 3 routes CDAB
+		Package() { 0x0002ffff, 0, 0, 18},
+		Package() { 0x0002ffff, 1, 0, 19},
+		Package() { 0x0002ffff, 2, 0, 16},
+		Package() { 0x0002ffff, 3, 0, 17},
+
+		// PCI Slot 4 routes ABCD
+		Package() { 0x0003ffff, 0, 0, 16},
+		Package() { 0x0003ffff, 1, 0, 17},
+		Package() { 0x0003ffff, 2, 0, 18},
+		Package() { 0x0003ffff, 3, 0, 19},
+
+		// PCI Slot 5 routes ABCD
+		Package() { 0x0004ffff, 0, 0, 16},
+		Package() { 0x0004ffff, 1, 0, 17},
+		Package() { 0x0004ffff, 2, 0, 18},
+		Package() { 0x0004ffff, 3, 0, 19},
+
+		// PCI Slot 6 routes BCDA
+		Package() { 0x0005ffff, 0, 0, 17},
+		Package() { 0x0005ffff, 1, 0, 18},
+		Package() { 0x0005ffff, 2, 0, 19},
+		Package() { 0x0005ffff, 3, 0, 16},
+
+		// FIXME: what's this supposed to mean? (adopted from ich7)
+		//Package() { 0x0008ffff, 0, 0, 20},
+	})
+} Else {
+	Return (Package() {
+		// PCI Slot 1 routes ABCD
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		// PCI Slot 2 routes BCDA
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		// PCI Slot 3 routes CDAB
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
+
+		// PCI Slot 4 routes ABCD
+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		// PCI Slot 5 routes ABCD
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		// PCI Slot 6 routes BCDA
+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		// FIXME
+		// Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+	})
+}
+
diff --git a/src/mainboard/roda/rk9/acpi/mainboard.asl b/src/mainboard/roda/rk9/acpi/mainboard.asl
new file mode 100644
index 0000000000..0837ed3130
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/mainboard.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LID0)
+{
+	Name(_HID, EisaId("PNP0C0D"))
+	Method(_LID, 0)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.LIDC)
+	}
+}
+
+Device (SLPB)
+{
+	Name(_HID, EisaId("PNP0C0E"))
+}
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+
+	// Wake
+	Name(_PRW, Package(){0x18, 0x04})
+}
+
+#include "acpi/battery.asl"
diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl
new file mode 100644
index 0000000000..b85433f798
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/platform.asl
@@ -0,0 +1,209 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// Call a trap so SMI can prepare for Sleep as well.
+	// TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4?
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	// TODO: Return Arg0 as second value if S-Arg0 was entered
+	// before.
+
+	Return(Package(){0,0})
+}
+
+// Power notification
+
+External (\_PR_.CPU0, DeviceObj)
+External (\_PR_.CPU1, DeviceObj)
+
+Method (PNOT)
+{
+	If (MPEN) {
+		If(And(PDC0, 0x08)) {
+			Notify (\_PR_.CPU0, 0x80)	 // _PPC
+
+			If (And(PDC0, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU0, 0x81) // _CST
+			}
+		}
+
+		If(And(PDC1, 0x08)) {
+			Notify (\_PR_.CPU1, 0x80)	 // _PPC
+			If (And(PDC1, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU1, 0x81) // _CST
+			}
+		}
+
+	} Else { // UP
+		Notify (\_PR_.CPU0, 0x80)
+		Sleep(0x64)
+		Notify(\_PR_.CPU0, 0x81)
+	}
+
+	// Notify the Batteries
+	Notify(BAT1, 0x80) // Execute BAT1 _BST
+	Notify(BAT2, 0x80) // Execute BAT2 _BST
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+	/* This method is placed on the top level, so we can make sure it's the
+	 * first executed _INI method.
+	 */
+	Method(_INI, 0)
+	{
+		/* The DTS data in NVS is probably not up to date.
+		 * Update temperature values and make sure AP thermal
+		 * interrupts can happen
+		 */
+
+		// TRAP(71) // TODO
+
+		/* Determine the Operating System and save the value in OSYS.
+		 * We have to do this in order to be able to work around
+		 * certain windows bugs.
+		 *
+		 *    OSYS value | Operating System
+		 *    -----------+------------------
+		 *       2000    | Windows 2000
+		 *       2001    | Windows XP(+SP1)
+		 *       2002    | Windows XP SP2
+		 *       2006    | Windows Vista
+		 *       ????    | Windows 7
+		 */
+
+		/* Let's assume we're running at least Windows 2000 */
+		Store (2000, OSYS)
+
+		If (CondRefOf(_OSI, Local0)) {
+			/* Linux answers _OSI with "True" for a couple of
+			 * Windows version queries. But unlike Windows it
+			 * needs a Video repost, so let's determine whether
+			 * we're running Linux.
+			 */
+
+			If (_OSI("Linux")) {
+				Store (1, LINX)
+			}
+
+			If (_OSI("Windows 2001")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP1")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP2")) {
+				Store (2002, OSYS)
+			}
+
+			If (_OSI("Windows 2006")) {
+				Store (2006, OSYS)
+			}
+		}
+
+		/* And the OS workarounds start right after we know what we're
+		 * running: Windows XP SP1 needs to have C-State coordination
+		 * enabled in SMM.
+		 */
+		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+			// TRAP(61) // TODO
+		}
+
+		/* SMM power state and C4-on-C3 settings need to be updated */
+		// TRAP(43) // TODO
+	}
+}
+
diff --git a/src/mainboard/roda/rk9/acpi/superio.asl b/src/mainboard/roda/rk9/acpi/superio.asl
new file mode 100644
index 0000000000..174f2f1062
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/superio.asl
@@ -0,0 +1,368 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* SMSC LPC47N227 */
+
+Device (SIO1)
+{
+	Name (_HID, EISAID("PNP0A05"))
+	Name (_UID, 1)
+
+	OperationRegion(SIOR, SystemIO, 0x2e, 0x02)
+	Field (SIOR, ByteAcc, Nolock, Preserve)
+	{
+		INDX,	8,
+		DATA,	8
+	}
+
+	Mutex (SIOM, 0x00)
+
+	Method (READ, 3)
+	{
+		Acquire (SIOM, 0xffff)
+		If (LEqual(Arg0, 0)) {
+			Store (0x55, INDX)
+			Store (Arg1, INDX)
+			Store (DATA, Local1)
+			Store (0xaa, INDX)
+		}
+		And (Local1, Arg2, Local1)
+		Release(SIOM)
+		Return(Local1)
+	}
+
+	Method (WRIT, 3)
+	{
+		Acquire (SIOM, 0xffff)
+		If (LEqual(Arg0, 0)) {
+			Store (0x55, INDX)
+			Store (Arg1, INDX)
+			Store (Arg2, DATA)
+			Store (0xaa, INDX)
+		}
+		Release(SIOM)
+	}
+
+	Device (COMA)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			// Device disabled by coreboot?
+			If (LEqual(CMAP, 0)) {
+				Return (0)
+			}
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x24, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x08), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x24, 0x00)
+
+			Store(READ(0, 0x28, 0x0f), Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x08, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+				IRQNoFlags() { 4 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x1)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8, _IOA)
+				IRQNoFlags(_IRA) { 4 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateWordField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN)
+			CreateWordField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX)
+			CreateWordField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ)
+
+			/* I/O Base */
+			Store (READ(0, 0x24, 0xfe), Local0)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOMN)
+			Store(Local0, IOMX)
+
+			/* Interrupt */
+			Store(READ(0, 0x28, 0xf0), Local0)
+			ShiftRight(Local0, 4, Local0)
+			ShiftLeft(1, Local0, IRQ)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x24, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+			ShiftLeft(Local0, 4, Local0)
+
+			Store(READ(0, 0x28, 0x0f), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x24, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x08, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x40, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x08, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x40, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x08, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+
+	Device (COMB)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 2)
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			// Device disabled by coreboot?
+			If (LEqual(CMBP, 0)) {
+				Return (0)
+			}
+
+			/* IRDA? */
+			Store(READ(0, 0x0c, 0x38), Local0)
+			If (LNotEqual(Local0, Zero)) {
+				Return (0)
+			}
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x25, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x80), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x25, 0x00)
+
+			Store(READ(0, 0x28, 0xf0), Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x80, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+				IRQNoFlags() { 3 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x1)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8, _IOB)
+				IRQNoFlags(_IRB) { 3 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateWordField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN)
+			CreateWordField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX)
+			CreateWordField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ)
+
+			/* I/O Base */
+			Store (READ(0, 0x25, 0xfe), Local0)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOMN)
+			Store(Local0, IOMX)
+
+			/* Interrupt */
+			Store(READ(0, 0x28, 0x0f), Local0)
+			ShiftLeft(1, Local0, IRQ)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x25, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+
+			Store(READ(0, 0x28, 0xf0), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x25, Local0)
+
+			Store(READ(0, 0x0c, 0xff), Local0)
+			Not(0x38, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x0c, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x80, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x20, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x80, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x20, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x80, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+}
+
diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl
new file mode 100644
index 0000000000..4cd888251a
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/thermal.asl
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	/* degree Celcius to deci-Kelvin (ACPI temperature unit) */
+	Method(C2dK, 1) {
+		Add (2732, Multiply (Arg0, 10), Local0)
+		Return (Local0)
+	}
+
+	ThermalZone (THRM)
+	{
+
+		// FIXME these could/should be read from the
+		// GNVS area, so they can be controlled by
+		// coreboot
+		Name(TC1V, 0x04)
+		Name(TC2V, 0x03)
+		Name(TSPV, 0x96)
+
+		// At which temperature should the OS start
+		// active cooling?
+		Method (_AC0, 0, Serialized)
+		{
+			Return (C2dK(120)) // Value for Rocky
+		}
+
+		// Critical shutdown temperature
+		Method (_CRT, 0, Serialized)
+		{
+			Return (C2dK(155)) // Value for Rocky
+		}
+
+		// CPU throttling start temperature
+		Method (_PSV, 0, Serialized)
+		{
+			Return (C2dK(105)) // Value for Rocky
+		}
+
+		// Get DTS Temperature
+		Method (_TMP, 0, Serialized)
+		{
+			If (\_SB.PCI0.LPCB.EC0.ALRC) {
+				Store(0, \_SB.PCI0.LPCB.EC0.ALRC)
+				Return(_AC0())
+			}
+
+			If (\_SB.PCI0.LPCB.EC0.ALRL) {
+				Store(0, THRO)
+				Store(0, \_SB.PCI0.LPCB.EC0.ALRL)
+			}
+
+			If (\_SB.PCI0.LPCB.EC0.ALRH) {
+				Store(1, THRO)
+				Store(0, \_SB.PCI0.LPCB.EC0.ALRH)
+			}
+
+			/* vendor BIOS reports 0K if TCPU >= 128 deg C ?!? */
+			Return (C2dK(\_SB.PCI0.LPCB.EC0.TCPU))
+		}
+
+
+		// Processors used for active cooling
+		Method (_PSL, 0, Serialized)
+		{
+			If (MPEN) {
+				Return (Package() {\_PR.CPU0, \_PR.CPU1})
+			}
+			Return (Package() {\_PR.CPU0})
+		}
+
+		// TC1 value for passive cooling
+		Method (_TC1, 0, Serialized)
+		{
+			Return (TC1V)
+		}
+
+		// TC2 value for passive cooling
+		Method (_TC2, 0, Serialized)
+		{
+			Return (TC2V)
+		}
+
+		// Sampling period for passive cooling
+		Method (_TSP, 0, Serialized)
+		{
+			Return (TSPV)
+		}
+
+
+	}
+}
+
diff --git a/src/mainboard/roda/rk9/acpi/video.asl b/src/mainboard/roda/rk9/acpi/video.asl
new file mode 100644
index 0000000000..507a390d27
--- /dev/null
+++ b/src/mainboard/roda/rk9/acpi/video.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+