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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-04 14:23:54 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 09:56:06 +0000 |
| commit | 4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch) | |
| tree | e9b31b8b64518a62f6a7885a1de54171471c918b /src/mainboard/roda/rk9 | |
| parent | 907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff) | |
| download | coreboot-4513020064cc4765e723f6f3cc2b8a45a0dc6545.tar.xz | |
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the
romstage C code.
Tested on Asus P5QC.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/roda/rk9')
| -rw-r--r-- | src/mainboard/roda/rk9/romstage.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 1bcfd622f0..b88671c705 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -30,7 +30,6 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> #include <superio/smsc/lpc47n227/lpc47n227.h> -#include <timestamp.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) @@ -107,7 +106,6 @@ static void default_superio_gpio_setup(void) /* Exit configuration state. */ pnp_exit_conf_state(sio); - /* Enable decoding of 0x600-0x60f through lpc. */ pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601); @@ -123,9 +121,6 @@ void mainboard_romstage_entry(unsigned long bist) int cbmem_initted; u16 reg16; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); |