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authorStefan Reinauer <stepan@coresystems.de>2010-04-12 23:04:29 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-12 23:04:29 +0000
commit3e1f524566dd89e5a7af424a06091e78c5a696da (patch)
tree9e1933a6caa17a92c5b767db7ec26f3f3a4ef451 /src/mainboard/roda
parent5934b507d5dcac9063ce180e0fa46be4cc01d69c (diff)
downloadcoreboot-3e1f524566dd89e5a7af424a06091e78c5a696da.tar.xz
move model_6ex car to a single file. No more .c files that only consist of a
single several pages long asm statement Could use some renumbering of post codes, but that's good for another time. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/roda')
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 28f56a89f3..c888871e5f 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -272,9 +272,8 @@ static void init_artec_dongle(void)
// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;