Add support for the Roda RK886EX a.k.a Rocky III+ ruggedised notebook

http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

32 files changed, 4707 insertions, 0 deletions

diff --git a/src/mainboard/roda/Kconfig b/src/mainboard/roda/Kconfig
new file mode 100644
index 0000000000..c2adb8c6f0
--- /dev/null
+++ b/src/mainboard/roda/Kconfig
@@ -0,0 +1,7 @@
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_RODA
+
+source "src/mainboard/roda/rk886ex/Kconfig"
+
+endchoice
diff --git a/src/mainboard/roda/rk886ex/Config.lb b/src/mainboard/roda/rk886ex/Config.lb
new file mode 100644
index 0000000000..259eb31a3c
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/Config.lb
@@ -0,0 +1,237 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+## 
+
+##
+## Only use the option table in a normal image
+##
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+
+##
+## Image size calculation
+##
+
+include /config/nofailovercalculation.lb
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+driver rtl8168.o
+object ec.o
+object m3885.o
+if CONFIG_GENERATE_MP_TABLE object mptable.o end
+if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
+
+if CONFIG_GENERATE_ACPI_TABLES
+	object fadt.o
+	object acpi_tables.o
+	makerule dsdt.c
+		depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+		action  "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD)  $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
+		action  "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
+		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
+	end
+	object ./dsdt.o
+end
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I.  -c $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+
+else
+
+makerule ./auto.inc
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
+	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+end
+
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+if CONFIG_USE_INIT
+	ldscript /cpu/x86/32bit/entry32.lds
+	ldscript /cpu/x86/car/cache_as_ram.lds
+end
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_USE_FALLBACK_IMAGE 
+        mainboardinit cpu/x86/16bit/reset16.inc
+        ldscript /cpu/x86/16bit/reset16.lds
+else
+        mainboardinit cpu/x86/32bit/reset32.inc
+        ldscript /cpu/x86/32bit/reset32.lds
+end
+
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
+
+###
+### This is the early phase of coreboot startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+##
+## Include the secondary Configuration files 
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i945
+
+        device apic_cluster 0 on
+                chip cpu/intel/socket_mFCPGA478
+                        device apic 0 on end
+                end
+        end
+
+        device pci_domain 0 on 
+                device pci 00.0 on end # host bridge
+		# auto detection:
+		#device pci 01.0 off end # i945 PCIe root port
+		#device pci 02.0 on end # vga controller
+		#device pci 02.1 on end # display controller
+
+                chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x0b"
+			register "pirqh_routing" = "0x0b"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "2"
+			register "gpi8_routing"  = "1"
+			register "gpi7_routing"  = "2"
+			register "gpe0_en" = "0x20800007"
+
+                        register "ide_legacy_combined" = "0x1"
+                        register "ide_enable_primary" = "0x1"
+                        register "ide_enable_secondary" = "0x0"
+                        register "sata_ahci" = "0x0"
+
+                	device pci 1b.0 on end # High Definition Audio
+                	device pci 1c.0 on end # PCIe
+                	device pci 1c.1 on end # PCIe
+                	device pci 1c.2 on end # PCIe
+			#device pci 1c.3 off end # PCIe port 4
+			#device pci 1c.4 off end # PCIe port 5
+			#device pci 1c.5 off end # PCIe port 6
+                	device pci 1d.0 on end # USB UHCI
+                	device pci 1d.1 on end # USB UHCI
+                	device pci 1d.2 on end # USB UHCI
+                	device pci 1d.3 on end # USB UHCI
+                	device pci 1d.7 on end # USB2 EHCI
+                	device pci 1e.0 on
+				chip southbridge/ti/pci7420
+                        		register "smartcard_enabled" = "0x0"
+					device pci 3.0 on end
+					device pci 3.1 on end
+					device pci 3.2 on end
+					device pci 3.3 off end  # smartcard
+				end
+			end # PCI bridge
+			#device pci 1e.2 off end # AC'97 Audio 
+			#device pci 1e.3 off end # AC'97 Modem
+                        device pci 1f.0 on # LPC bridge
+                                chip superio/smsc/lpc47n227
+					device pnp 2e.1 off # Parallel port
+					end
+					device pnp 2e.2 on # COM1
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+					end
+					device pnp 2e.3 on # COM2
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+					end
+					device pnp 2e.5 off # Keyboard+Mouse
+					#	 io 0x60 = 0x60
+					#	 io 0x62 = 0x64
+					#	irq 0x70 = 1
+					#	irq 0x72 = 12
+					end
+                                end
+				chip superio/renesas/m3885x
+					device pnp ff.1 on # dummy address
+					end
+				end
+
+                        end
+			#device pci 1f.1 off end # IDE
+                        device pci 1f.2 on end  # SATA
+                        device pci 1f.3 on end  # SMBus
+			#device pci 1f.4 off end # Realtek ID Codec
+                end
+        end
+end
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
new file mode 100644
index 0000000000..4f1f8727fd
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -0,0 +1,64 @@
+config BOARD_RODA_RK886EX
+	bool "RK886EX"
+	select ARCH_X86
+	select CPU_INTEL_CORE
+	select CPU_INTEL_SOCKET_MFCPGA478
+	select NORTHBRIDGE_INTEL_I945
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select SOUTHBRIDGE_TI_PCI7420
+	select SUPERIO_SMSC_LPC47N227
+	select SUPERIO_RENESAS_M3885X
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select MMCONF_SUPPORT
+	select USE_PRINTK_IN_CAR
+	select AP_IN_SIPI_WAIT
+	select UDELAY_LAPIC
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select BOARD_ROMSIZE_KB_1024
+
+config MAINBOARD_DIR
+	string
+	default roda/rk886ex
+	depends on BOARD_RODA_RK886EX
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+	depends on BOARD_RODA_RK886EX
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_RODA_RK886EX
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_RODA_RK886EX
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_RODA_RK886EX
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "RK886EX"
+	depends on BOARD_RODA_RK886EX
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+	depends on BOARD_RODA_RK886EX
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+	depends on BOARD_RODA_RK886EX
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_RODA_RK886EX
diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc
new file mode 100644
index 0000000000..ff8d072e7c
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/Makefile.inc
@@ -0,0 +1,72 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+driver-y += mainboard.o
+driver-y += m3885.o
+driver-y += ec.o
+driver-y += rtl8168.o
+
+obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
+obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o
+
+smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	$(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src)/mainboard/$(MAINBOARDDIR) $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl -o $(obj)/dsdt.asl
+	iasl -p dsdt -tc $(obj)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
diff --git a/src/mainboard/roda/rk886ex/Options.lb b/src/mainboard/roda/rk886ex/Options.lb
new file mode 100644
index 0000000000..735223272c
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/Options.lb
@@ -0,0 +1,339 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+# Tables
+uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_GENERATE_PIRQ_TABLE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_GENERATE_ACPI_TABLES
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
+uses CONFIG_HAVE_ACPI_RESUME
+# SMP
+uses CONFIG_SMP
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_AP_IN_SIPI_WAIT
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+# Image Size
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+# Payload
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+# Build Internals
+uses CONFIG_RAMBASE
+uses CONFIG_ROMBASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_SMI_HANDLER
+uses CONFIG_PCIE_CONFIGSPACE_HOLE
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_MMCONF_BASE_ADDRESS
+uses CONFIG_GFXUMA
+#
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+# Timers
+uses CONFIG_UDELAY_LAPIC
+# Console
+uses CONFIG_USBDEBUG_DIRECT
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
+uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+uses CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
+uses CONFIG_DEBUG
+# Toolchain
+uses CC
+uses HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
+# Tweaks
+uses CONFIG_GDB_STUB
+uses CONFIG_MAX_REBOOT_CNT
+uses CONFIG_USE_WATCHDOG_ON_BOOT
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+
+###
+### Build options
+###
+
+##
+##
+default CONFIG_MAX_REBOOT_CNT=3
+
+##
+## Use the watchdog to break out of a lockup condition
+##
+default CONFIG_USE_WATCHDOG_ON_BOOT=0
+
+##
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+##
+default CONFIG_ROM_SIZE=1024*1024
+
+
+##
+## Build code for the fallback boot
+##
+default CONFIG_HAVE_FALLBACK_BOOT=1
+
+##
+## Delay timer options
+## 
+default CONFIG_UDELAY_LAPIC=1
+
+##
+## Build code to reset the motherboard from coreboot
+##
+default CONFIG_HAVE_HARD_RESET=1
+
+##
+## Build SMI handler
+##
+default CONFIG_HAVE_SMI_HANDLER=1
+
+##
+## Leave a hole for mmapped PCIe config space
+##
+
+default CONFIG_PCIE_CONFIGSPACE_HOLE=1
+default CONFIG_MMCONF_SUPPORT=1
+default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+##
+## UMA
+##
+default CONFIG_GFXUMA=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default CONFIG_GENERATE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=18
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default CONFIG_GENERATE_MP_TABLE=1
+
+##
+## Build code to provide ACPI support
+##
+default CONFIG_GENERATE_ACPI_TABLES=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
+default CONFIG_HAVE_ACPI_RESUME=1
+
+##
+## Build code to export a CMOS option table
+##
+default CONFIG_HAVE_OPTION_TABLE=1
+
+##
+## Move the default CONFIG_coreboot cmos range off of AMD RTC registers
+##
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=0
+default CONFIG_PCI_ROM_RUN=0
+#default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
+#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0
+# This is needed for Intel's IGD design:
+#default CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=1
+#default CONFIG_DEBUG=0
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+default CONFIG_AP_IN_SIPI_WAIT=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+##
+## Execute In Place settings
+##
+
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default CONFIG_MAINBOARD_PART_NUMBER="RK886EX"
+default CONFIG_MAINBOARD_VENDOR=     "RODA"
+
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x4352
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6886
+
+###
+### coreboot layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 32K stack
+##
+default CONFIG_STACK_SIZE=0x8000
+
+##
+## Use a small 32K heap
+##
+default CONFIG_HEAP_SIZE=0x8000
+
+
+###
+### Compute the location and size of where this firmware image
+### (coreboot plus bootloader) will live in the boot rom chip.
+###
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+
+##
+## coreboot C code runs at this location in RAM
+##
+default CONFIG_RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD=1
+
+###
+### Defaults of options that you may want to override in the target config file
+### 
+
+##
+## The default compiler
+##
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=1
+
+##
+## USB debug console
+##
+
+default CONFIG_USBDEBUG_DIRECT=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
+
+# Select the serial console base port
+default CONFIG_TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default CONFIG_TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
+
+##
+## Select power on after power fail setting
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end
diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl
new file mode 100644
index 0000000000..77269ad143
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/battery.asl
@@ -0,0 +1,339 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name(\CBA1, 0x60)
+Name(\CBA2, 0x60)
+
+Device (BAT1)
+{
+	Name(_HID, EisaId("PNP0C0A"))
+	Name(_UID, 1)
+
+	Name(_PCL, Package(){ _SB })
+	Name(PSTA, 0x1f)
+	Name(PBIF, Package() {
+		0x00,
+		0x78,
+		0x64,
+		0x01,
+		0x2b5c,	// Capacity?
+		0x05,
+		0x03,
+		0x01,
+		0x01,
+		"???",	// Name
+		"???",	// Number
+		"???",	// Type
+		"???"	// Vendor
+	})
+	Name(PBST, Package() { 0x01, 0x16, 0x64, 0x2b5c })
+
+	/* Status */
+	Method(_STA, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			If(\_SB.PCI0.LPCB.EC0.P62S) {
+				Return(0x0f)
+			} Else {
+				Return(0x1f)
+			}
+		} Else {
+			Return(0x0f)
+		}
+	}
+
+	/* Battery Info */
+	Method(_BIF, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			If(\_SB.PCI0.LPCB.EC0.P62S) {
+				IVBI()
+				IVBS()
+			} Else {
+				UPBI()
+			}
+		}
+
+		Return(PBIF)
+	}
+
+	/* Battery Status */
+	Method(_BST, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			UPBS()
+		}
+
+		Return(PBST)
+	}
+
+	/* Update Battery Info */
+	Method(UPBI, 0)
+	{
+		Store (0x78, Index(PBIF, 1))
+		Store (0x64, Index(PBIF, 2))
+		Store (0x2b5c, Index(PBIF, 4))
+		Store ("Bat1", Index(PBIF, 9))
+		Store ("001", Index(PBIF, 10))
+		Store ("LION", Index(PBIF, 11))
+		Store ("Panasonic", Index(PBIF, 12))
+	}
+
+	Method(UPBS, 0)
+	{
+		Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0)
+		If (Not(Local0)) {
+			Store(0, GP38)
+			Sleep(0x64)
+			Store(GP38, Local0)
+			If (Not(Local0)) {
+				Store (RDW(0x0d), Local0)
+				If (LNotEqual(Local0, 0xeeee)) {
+					If (LLessEqual(Local0, 0x64)) {
+						Store(Local0, CBA1)
+					}
+				}
+			}
+		}
+		
+		Store (CBA1, Local0)
+		Store (Local0, Index(PBST, 2))
+		Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3))
+		Store (0, Local1)
+
+		If (PWRS) {
+			If (LLess(Local0, 0x64)) {
+				Store (2, Local1)
+			}
+		} Else {
+			If (LLessEqual(Local0, 0x5)) {
+				Store (4, Local1)
+			} Else {
+				Store (1, Local1)
+			}
+		}
+		
+		Store (Local1, Index(PBST, 0))
+		If (\_SB.PCI0.LPCB.EC0.P63S) {
+			Store (0x16, Index(PBST, 1))
+		} Else  {
+			Store (0x0b, Index(PBST, 1))
+		}
+	}
+
+	// Invalidate Battery Info
+	Method(IVBI, 0)
+	{
+		Store (0xffffffff, Index(PBIF, 1))
+		Store (0xffffffff, Index(PBIF, 2))
+		Store (0xffffffff, Index(PBIF, 4))
+		Store ("Bad", Index(PBIF, 9))
+		Store ("Bad", Index(PBIF, 10))
+		Store ("Bad", Index(PBIF, 11))
+		Store ("Bad", Index(PBIF, 12))
+		Store (1, PBIF)
+	}
+
+	Method(IVBS, 0)
+	{
+		Store (0x0, Index(PBST, 0))
+		Store (0xffffffff, Index(PBST, 1))
+		Store (0xffffffff, Index(PBST, 2))
+		Store (0xffffffff, Index(PBST, 3))
+	}
+}
+
+
+Device (BAT2)
+{
+	Name(_HID, EisaId("PNP0C0A"))
+	Name(_UID, 2)
+
+	Name(_PCL, Package(){ _SB })
+	Name(PSTA, 0x1f)
+	Name(PBIF, Package() {
+		0x00,
+		0x78,
+		0x64,
+		0x01,
+		0x2b5c,	// Capacity?
+		0x05,
+		0x03,
+		0x01,
+		0x01,
+		"???",	// Name
+		"???",	// Number
+		"???",	// Type
+		"???"	// Vendor
+	})
+	Name(PBST, Package() { 0x01, 0x16, 0x64, 0x2b5c })
+
+	/* Status */
+	Method(_STA, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			If(\_SB.PCI0.LPCB.EC0.P63S) {
+				Return(0x0f)
+			} Else {
+				Return(0x1f)
+			}
+		} Else {
+			Return(0x0f)
+		}
+	}
+
+	/* Battery Info */
+	Method(_BIF, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			If(\_SB.PCI0.LPCB.EC0.P63S) {
+				IVBI()
+				IVBS()
+			} Else {
+				UPBI()
+			}
+		}
+
+		Return(PBIF)
+	}
+
+	/* Battery Status */
+	Method(_BST, 0)
+	{
+		If(\_SB.PCI0.LPCB.EC0.ECON) {
+			UPBS()
+		}
+
+		Return(PBST)
+	}
+
+	/* Update Battery Info */
+	Method(UPBI, 0)
+	{
+		Store (0x78, Index(PBIF, 1))
+		Store (0x64, Index(PBIF, 2))
+		Store (0x2b5c, Index(PBIF, 4))
+		Store ("Bat2", Index(PBIF, 9))
+		Store ("002", Index(PBIF, 10))
+		Store ("LION", Index(PBIF, 11))
+		Store ("Panasonic", Index(PBIF, 12))
+	}
+
+	Method(UPBS, 0)
+	{
+		Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0)
+		If (Not(Local0)) {
+			Store(0, GP38)
+			Sleep(0x64)
+			Store(GP38, Local0)
+			If (Not(Local0)) {
+				Store (RDW(0x0d), Local0)
+				If (LNotEqual(Local0, 0xeeee)) {
+					If (LLessEqual(Local0, 0x64)) {
+						Store(Local0, CBA2)
+					}
+				}
+			}
+		}
+		
+		Store (CBA2, Local0)
+		Store (Local0, Index(PBST, 2))
+		Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3))
+		Store (0, Local1)
+
+		If (PWRS) {
+			If (LLess(Local0, 0x64)) {
+				Store (2, Local1)
+			}
+		} Else {
+			If (LLessEqual(Local0, 0x5)) {
+				Store (4, Local1)
+			} Else {
+				Store (1, Local1)
+			}
+		}
+		
+		Store (Local1, Index(PBST, 0))
+		If (\_SB.PCI0.LPCB.EC0.P62S) {
+			Store (0x16, Index(PBST, 1))
+		} Else  {
+			Store (0x0b, Index(PBST, 1))
+		}
+	}
+
+	// Invalidate Battery Info
+	Method(IVBI, 0)
+	{
+		Store (0xffffffff, Index(PBIF, 1))
+		Store (0xffffffff, Index(PBIF, 2))
+		Store (0xffffffff, Index(PBIF, 4))
+		Store ("Bad", Index(PBIF, 9))
+		Store ("Bad", Index(PBIF, 10))
+		Store ("Bad", Index(PBIF, 11))
+		Store ("Bad", Index(PBIF, 12))
+		Store (1, PBIF)
+	}
+
+	Method(IVBS, 0)
+	{
+		Store (0x0, Index(PBST, 0))
+		Store (0xffffffff, Index(PBST, 1))
+		Store (0xffffffff, Index(PBST, 2))
+		Store (0xffffffff, Index(PBST, 3))
+	}
+}
+
+Method (RDW, 1)
+{
+	Store (0x16, \_SB.PCI0.LPCB.EC0.SMAD)
+	Store (Arg0, \_SB.PCI0.LPCB.EC0.SMCM)
+	Store (0x09, \_SB.PCI0.LPCB.EC0.SMPR)
+	While (LNotEqual(\_SB.PCI0.LPCB.EC0.SMPR, 0x00)) {
+		Stall (1)
+	}
+
+	Return (\_SB.PCI0.LPCB.EC0.SMW0)
+}
+
+Device (ADP1)
+{
+	Name (_HID, "ACPI0003")
+	Method (_PSR, 0)
+	{
+		If (\_SB.PCI0.LPCB.EC0.ECON) {
+			Store (\_SB.PCI0.LPCB.EC0.P60S, Local0)
+			If (Local0) {
+				Store (0, PWRS)
+			} Else {
+				Store (1, PWRS)
+			}
+		}
+
+		Stall (0x02)
+		Return (PWRS)
+	}
+
+	Method (_PCL, 0)
+	{
+		Return (_SB)
+	}
+}
+
diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl
new file mode 100644
index 0000000000..2b8c7ea429
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/ec.asl
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 1)
+
+	Name (_GPE, 23)	// GPI07 / GPE23 -> Runtime SCI
+	Name (ECON, 0)
+	Name (QEVT, 0)
+
+	OperationRegion(ERAM, EmbeddedControl, 0x00, 0xff)
+	Field (ERAM, ByteAcc, NoLock, Preserve)
+	{
+		Offset(0x04), // Command interface
+		CMCM,	  8,
+		CMD1,	  8,
+		CMD2,	  8,
+		CMD3,	  8,
+		Offset(0x18), // SMBus
+		SMPR,	  8,
+		SMST,	  8,
+		SMAD,	  8,
+		SMCM,	  8,
+		Offset(0x1c),
+		SMW0,	 16,
+		//SMD0,	264,
+		Offset(0x3d),
+		SMAA,	  8,
+		Offset(0x78), // GPIs
+		P60S,	  1,
+		P61S,	  1,
+		P62S,	  1,
+		P63S,	  1,
+		P64S,	  1,
+		P65S,	  1,
+		P66S,	  1,
+		P67S,	  1,
+		Offset(0x83), // Thermal
+		RTMP,	  8,
+		TML0,	  8,
+		TMH0,	  8,
+		Offset(0x87),
+		TMCR,	  8,
+		Offset(0x89),
+		TML1,	  8,
+		TMH1,	  8
+	}
+
+	Method (_CRS, 0)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 1, 1)
+			IO (Decode16, 0x66, 0x66, 1, 1)
+		})
+
+		Return (ECMD)
+	}
+
+	Method (_REG, 2)
+	{
+		// This method is needed by Windows XP/2000 for
+		// EC initialization before a driver is loaded
+	
+		If (LEqual(Arg0, 0x03)) {
+			Store (Arg1, ECON)
+		}
+	}
+
+	// EC Query methods
+	
+	Method (_Q11, 0)
+	{
+		Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug)
+		Notify(SLPB, 0x80)
+	}
+
+	Method (_Q12, 0)
+	{
+		Store("_Q12: Fn-F9 (Display Switch) pressed", Debug)
+		// Store(1, TLST)
+		// HKDS(10)
+	}
+
+	Method (_Q30, 0)
+	{
+		Store("_Q30: AC In/Out", Debug)
+		Notify(ADP1, 0x80)	// Tell the Power Adapter
+		PNOT()			// and the CPU and Battery
+	}
+
+	Method (_Q31, 0)
+	{
+		Store("_Q31: LID Open/Close", Debug)
+		Notify(LID0, 0x80)
+	}
+
+	Method (_Q32, 0)
+	{
+		Store("_Q32: Battery 1 In/Out", Debug)
+		If (ECON) {
+			Store (P62S, Local0)
+			If (Not(Local0)) {
+				Notify(BAT1, 0x80)
+			}
+		}
+	}
+
+	Method (_Q33, 0)
+	{
+		Store("_Q33: Battery 2 In/Out", Debug)
+		If (ECON) {
+			Store (P63S, Local0)
+			If (Not(Local0)) {
+				Notify(BAT2, 0x80)
+			}
+		}
+	}
+
+	Method (_Q34, 0)
+	{
+		Store("_Q34: LPT/FDD", Debug)
+		// PHSS(0x70)
+	}
+
+	Method (_Q35, 0)
+	{
+		Store("_Q35: Processor is hot", Debug)
+	}
+
+	Method (_Q36, 0)
+	{
+		Store("_Q36: Thermal Warning", Debug)
+	}
+
+	Method (_Q37, 0)
+	{
+		Store("_Q37: PME", Debug)
+	}
+
+	Method (_Q38, 0)
+	{
+		Store("_Q38: Thermal", Debug)
+	}
+
+	Method (_Q39, 0)
+	{
+		Store("_Q39: Thermal", Debug)
+	}
+
+	// TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/roda/rk886ex/acpi/gpe.asl b/src/mainboard/roda/rk886ex/acpi/gpe.asl
new file mode 100644
index 0000000000..34711271a2
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/gpe.asl
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (_GPE)
+{
+	/* The event numbers correspond to the bit numbers in the
+	 * GPE0_EN register PMBASE + 0x2C.
+	 */
+
+	// Thermal Event
+	Method (_L00, 0)
+	{
+
+	}
+
+	// Hot Plug
+	Method (_L01, 0)
+	{
+
+	}
+
+	// Software GPE
+	Method (_L02, 0)
+	{
+
+	}
+
+	// USB1
+	Method (_L03, 0)
+	{
+
+	}
+
+	// USB2
+	Method (_L04, 0)
+	{
+
+	}
+
+	// AC97
+	Method (_L05, 0)
+	{
+
+	}
+
+	// _L06 TCOSCI
+
+	// SMBus (Reserved!)
+	Method (_L07, 0)
+	{
+
+	}
+
+	// COM1/COM2 (RI)
+	Method (_L08, 0)
+	{
+
+	}
+
+	// PCIe
+	Method (_L09, 0)
+	{
+
+	}
+
+	// _L0A BatLow / Quick Resume
+
+	// PME
+	Method (_L0B, 0)
+	{
+
+	}
+
+	// USB3
+	Method (_L0C, 0)
+	{
+
+	}
+
+	// PME B0
+	Method (_L0D, 0)
+	{
+
+	}
+
+	// USB4
+	Method (_L0E, 0)
+	{
+
+	}
+
+	// _L10 - _L1f: GPIn
+
+	// GPI13
+	Method (_L1D, 0)
+	{
+
+	}
+}
diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000000..6a16b5b887
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the 
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, 0, 16 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 16 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, 0, 23 },
+			Package() { 0x001dffff, 1, 0, 19 },
+			Package() { 0x001dffff, 2, 0, 18 },
+			Package() { 0x001dffff, 3, 0, 16 },
+			// AC97				0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, 0, 22 },
+			Package() { 0x001effff, 1, 0, 20 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, 0, 18 },
+			Package() { 0x001fffff, 1, 0, 19 },
+			Package() { 0x001fffff, 1, 0, 20 },
+			Package() { 0x001fffff, 3, 0, 16 }
+		})
+	} Else {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			// AC97				0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+		})
+	}
+}
+
diff --git a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..4c4edd7c17
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the 
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		// PCI Slot 1 routes ????
+		Package() { 0x0000ffff, 0, 0, 21},
+		Package() { 0x0000ffff, 1, 0, 22},
+		Package() { 0x0000ffff, 2, 0, 23},
+		Package() { 0x0000ffff, 3, 0, 20},
+
+		// PCI Slot 2 routes ????
+		Package() { 0x0001ffff, 0, 0, 22},
+		Package() { 0x0001ffff, 1, 0, 21},
+		Package() { 0x0001ffff, 2, 0, 20},
+		Package() { 0x0001ffff, 3, 0, 23},
+
+		// PCI Slot 3 routes ????
+		Package() { 0x0002ffff, 0, 0, 18},
+		Package() { 0x0002ffff, 1, 0, 19},
+		Package() { 0x0002ffff, 2, 0, 17},
+		Package() { 0x0002ffff, 3, 0, 16},
+
+		Package() { 0x0003ffff, 0, 0, 16},
+		Package() { 0x0003ffff, 1, 0, 17},
+		Package() { 0x0003ffff, 2, 0, 18},
+		Package() { 0x0003ffff, 3, 0, 19},
+
+		Package() { 0x0005ffff, 0, 0, 17},
+		Package() { 0x0005ffff, 1, 0, 20},
+		Package() { 0x0005ffff, 2, 0, 22},
+		Package() { 0x0005ffff, 3, 0, 21},
+
+		Package() { 0x0008ffff, 0, 0, 20},
+	})
+} Else {
+	Return (Package() {
+		// PCI Slot 1 routes FGHE
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+		// PCI Slot 2 routes GFEH
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+		// PCI Slot 3 routes CDBA
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+		Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+	})
+}
+
diff --git a/src/mainboard/roda/rk886ex/acpi/mainboard.asl b/src/mainboard/roda/rk886ex/acpi/mainboard.asl
new file mode 100644
index 0000000000..7a2dea76a2
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/mainboard.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LID0)
+{
+	Name(_HID, EisaId("PNP0C0D"))
+	Method(_LID, 0)
+	{
+		Return (1)
+	}
+}
+
+Device (SLPB)
+{
+	Name(_HID, EisaId("PNP0C0E"))
+}
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+	
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x04})
+}
+
+#include "acpi/battery.asl"
diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl
new file mode 100644
index 0000000000..9e86d0b7a7
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/platform.asl
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt 
+ * routing via the i8259 interrupt controller or the APIC.
+ * 
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// Call a trap so SMI can prepare for Sleep as well.
+	// TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3? 
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4? 
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	Return(Package(){0,0})
+}
+
+// Power notification
+
+External (\_PR_.CPU0, DeviceObj)
+External (\_PR_.CPU1, DeviceObj)
+
+Method (PNOT)
+{
+	If (MPEN) {
+		If(And(PDC0, 0x08)) {
+			Notify (\_PR_.CPU0, 0x80)	 // _PPC
+
+			If (And(PDC0, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU0, 0x81) // _CST
+			}
+		}
+
+		If(And(PDC1, 0x08)) {
+			Notify (\_PR_.CPU1, 0x80)	 // _PPC
+			If (And(PDC1, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU1, 0x81) // _CST
+			}
+		}
+
+	} Else { // UP
+		Notify (\_PR_.CPU0, 0x80)
+		Sleep(0x64)
+		Notify(\_PR_.CPU0, 0x81)
+	}
+
+	// Notify the Batteries
+	Notify(BAT1, 0x80) // Execute BAT1 _BST
+	Notify(BAT2, 0x80) // Execute BAT2 _BST
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+	/* This method is placed on the top level, so we can make sure it's the
+	 * first executed _INI method.
+	 */
+	Method(_INI, 0)
+	{
+		/* The DTS data in NVS is probably not up to date.
+		 * Update temperature values and make sure AP thermal
+		 * interrupts can happen
+		 */
+
+		// TRAP(71) // TODO
+
+		/* Determine the Operating System and save the value in OSYS.
+		 * We have to do this in order to be able to work around
+		 * certain windows bugs.
+		 *
+		 *    OSYS value | Operating System
+		 *    -----------+------------------
+		 *       2000    | Windows 2000
+		 *       2001    | Windows XP(+SP1)
+		 *       2002    | Windows XP SP2
+		 *       2006    | Windows Vista
+		 *       ????    | Windows 7
+		 */
+
+		/* Let's assume we're running at least Windows 2000 */
+		Store (2000, OSYS)
+
+		If (CondRefOf(_OSI, Local0)) {
+			/* Linux answers _OSI with "True" for a couple of
+			 * Windows version queries. But unlike Windows it
+			 * needs a Video repost, so let's determine whether
+			 * we're running Linux.
+			 */
+
+			If (_OSI("Linux")) {
+				Store (1, LINX)
+			}
+
+			If (_OSI("Windows 2001")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP1")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP2")) {
+				Store (2002, OSYS)
+			}
+
+			If (_OSI("Windows 2006")) {
+				Store (2006, OSYS)
+			}
+		}
+
+		/* And the OS workarounds start right after we know what we're
+		 * running: Windows XP SP1 needs to have C-State coordination
+		 * enabled in SMM.
+		 */
+		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+			// TRAP(61) // TODO
+		}
+
+		/* SMM power state and C4-on-C3 settings need to be updated */
+		// TRAP(43) // TODO
+	}
+}
+
diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl
new file mode 100644
index 0000000000..67ff1f91f7
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/superio.asl
@@ -0,0 +1,379 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* SMSC LPC47N227 */
+
+Device (SIO1)
+{
+	Name (_HID, EISAID("PNP0A05"))
+	Name (_UID, 1)
+
+	OperationRegion(SIOR, SystemIO, 0x2e, 0x02)
+	Field (SIOR, ByteAcc, Nolock, Preserve)
+	{
+		INDX,	8,
+		DATA,	8
+	}
+
+	Mutex (SIOM, 0x00)
+
+	Method (READ, 3)
+	{
+		Acquire (SIOM, 0xffff)
+		If (LEqual(Arg0, 0)) {
+			Store (0x55, INDX)
+			Store (Arg1, INDX)
+			Store (DATA, Local1)
+			Store (0xaa, INDX)
+		}
+		And (Local1, Arg2, Local1)
+		Release(SIOM)
+		Return(Local1)
+	}
+
+	Method (WRIT, 3)
+	{
+		Acquire (SIOM, 0xffff)
+		If (LEqual(Arg0, 0)) {
+			Store (0x55, INDX)
+			Store (Arg1, INDX)
+			Store (Arg2, DATA)
+			Store (0xaa, INDX)
+		}
+		Release(SIOM)
+	}
+
+	Device (COMA)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			// Device disabled by coreboot?
+			If (LEqual(CMAP, 0)) {
+				Return (0)
+			}
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x24, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x08), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x24, 0x00)
+
+			Store(READ(0, 0x28, 0x0f), Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x08, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+				IRQNoFlags() { 4 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x0)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8, _IOA)
+				IRQNoFlags(_IRA) { 4 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOLO)
+			CreateByteField(RSRC, 0x03, IOHI) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IORL)
+			CreateByteField(RSRC, 0x05, IORH) // Why?
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQL)
+			
+			Store (READ(0, 0x24, 0xff), Local0)
+			And (Local0, 0xc0, Local1)
+			ShiftRight(Local1, 0x06, Local1)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOLO)
+			Store(Local1, IOHI)
+			Store(IOLO, IORL)
+			Store(IOHI, IORH)
+
+			/* Interrupt */
+			Store(READ(0, 0x28, 0xf0), Local0)
+			ShiftRight(Local0, 4, Local0)
+			ShiftLeft(1, Local0, IRQL)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x24, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+			ShiftLeft(Local0, 4, Local0)
+
+			Store(READ(0, 0x28, 0x0f), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x24, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x08, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x40, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x08, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x40, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x08, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+
+	Device (COMB)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 2)
+		Name(_PRW, Package() { 0x08, 0x03 })
+
+		/* Device Status */
+		Method (_STA, 0)
+		{
+			// Device disabled by coreboot?
+			If (LEqual(CMBP, 0)) {
+				Return (0)
+			}
+
+			/* IRDA? */
+			Store(READ(0, 0x0c, 0x38), Local0)
+			If (LNotEqual(Local0, Zero)) {
+				Return (0)
+			}
+
+			// Is the hardware enabled?
+			Store (READ(0, 0x25, 0xff), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (0xd)
+			} Else {
+				// Power Enabled?
+				Store (READ(0, 0x02, 0x80), Local0)
+				If (LEqual(Local0, 0)) {
+					Return (0x0d)
+				} Else {
+					Return (0x0f)
+				}
+			}
+		}
+
+		/* Device Disable */
+		Method (_DIS, 0)
+		{
+			WRIT(0, 0x25, 0x00)
+
+			Store(READ(0, 0x28, 0xf0), Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x80, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+
+		/* Possible Resource Settings */
+		Name(_PRS, ResourceTemplate() {
+			StartDependentFn(0, 1) {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+				IRQNoFlags() { 3 }
+			} EndDependentFn()
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0)
+		{
+			Name(NONE, ResourceTemplate() {
+				IO(Decode16, 0x000, 0x000, 0x0, 0x0)
+				IRQNoFlags() { }
+			})
+
+			Name(RSRC, ResourceTemplate() {
+				IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8, _IOB)
+				IRQNoFlags(_IRB) { 3 }
+			})
+
+			And (_STA(), 0x02, Local0)
+			If (LEqual(Local0, 0)) {
+				Return(NONE)
+			}
+
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMB._CRS._IOB._MIN, IOLO)
+			CreateByteField(RSRC, 0x03, IOHI)
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMB._CRS._IOB._MAX, IORL)
+			CreateByteField(RSRC, 0x05, IORH)
+			CreateByteField(RSRC,
+				\_SB.PCI0.LPCB.SIO1.COMB._CRS._IRB._INT, IRQL)
+			
+			Store (READ(0, 0x25, 0xff), Local0)
+			And (Local0, 0xc0, Local1)
+			ShiftRight(Local1, 0x06, Local1)
+			ShiftLeft(Local0, 0x02, Local0)
+			Store(Local0, IOLO)
+			Store(Local1, IOHI)
+			Store(IOLO, IORL)
+			Store(IOHI, IORH)
+
+			/* Interrupt */
+			Store(READ(0, 0x28, 0x0f), Local0)
+			ShiftRight(Local0, 4, Local0)
+			ShiftLeft(1, Local0, IRQL)
+			Return(RSRC)
+		}
+
+		/* Set Resource Settings */
+		Method(_SRS, 1)
+		{
+			CreateByteField(Arg0, 0x02, IOLO)
+			CreateByteField(Arg0, 0x03, IOHI)
+			CreateByteField(Arg0, 0x09, IRQL)
+
+			WRIT(0, 0x25, 0)
+			FindSetRightBit(IRQL, Local0)
+			Decrement(Local0)
+
+			Store(READ(0, 0x28, 0xf0), Local1)
+			Or(Local0, Local1, Local0)
+			WRIT(0, 0x28, Local0)
+
+			Store(IOLO, Local0)
+			ShiftRight(Local0, 2, Local0)
+			And(Local0, 0xfe, Local0)
+
+			Store(IOHI, Local1)
+			ShiftLeft(Local1, 6, Local1)
+			Or (Local0, Local1, Local0)
+			WRIT(0, 0x25, Local0)
+
+			Store(READ(0, 0x0c, 0xff), Local0)
+			Not(0x38, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x0c, Local0)
+
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x80, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store(READ(0, 0x07, 0xff), Local0)
+			Not(0x20, Local1)
+			And (Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D0 state - Line drivers are on */
+		Method (_PS0, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Or(Local0, 0x80, Local0)
+			WRIT(0, 0x02, Local0)
+
+			Store (READ(0, 0x07, 0xff), Local0)
+			Not(0x20, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x07, Local0)
+		}
+
+		/* D3 State - Line drivers are off */
+		Method(_PS3, 0)
+		{
+			Store(READ(0, 0x02, 0xff), Local0)
+			Not(0x80, Local1)
+			And(Local0, Local1, Local0)
+			WRIT(0, 0x02, Local0)
+		}
+	}
+}
+
diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl
new file mode 100644
index 0000000000..cea3e8ea7b
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+
+		// FIXME these could/should be read from the
+		// GNVS area, so they can be controlled by 
+		// coreboot
+		Name(TC1V, 0x04)
+		Name(TC2V, 0x03)
+		Name(TSPV, 0x64)
+
+		// At which temperature should the OS start
+		// active cooling?
+		Method (_AC0, 0, Serialized)
+		{
+			Return (0xf5c) // Value for Rocky
+		}
+
+		// Method (_AC1, 0, Serialized)
+		// {
+		// 	Return (0xf5c)
+		// }
+
+		// Critical shutdown temperature
+		Method (_CRT, 0, Serialized)
+		{
+			Return (Add (0x0aac, 0x50)) // FIXME
+		}
+
+		// CPU throttling start temperature
+		Method (_PSV, 0, Serialized)
+		{
+			Return (0xaaf) // FIXME
+		}
+
+		// Get DTS Temperature
+		Method (_TMP, 0, Serialized)
+		{
+			Return (0xaac) // FIXME
+		}
+
+		// Processors used for active cooling
+		Method (_PSL, 0, Serialized)
+		{
+			If (MPEN) {
+				Return (Package() {\_PR.CPU0, \_PR.CPU1})
+			}
+			Return (Package() {\_PR.CPU0})
+		}
+
+		// TC1 value for passive cooling
+		Method (_TC1, 0, Serialized)
+		{
+			Return (TC1V)
+		}
+
+		// TC2 value for passive cooling
+		Method (_TC2, 0, Serialized)
+		{
+			Return (TC2V)
+		}
+
+		// Sampling period for passive cooling
+		Method (_TSP, 0, Serialized)
+		{
+			Return (TSPV)
+		}
+
+
+	}
+}
+
diff --git a/src/mainboard/roda/rk886ex/acpi/video.asl b/src/mainboard/roda/rk886ex/acpi/video.asl
new file mode 100644
index 0000000000..507a390d27
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi/video.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
new file mode 100644
index 0000000000..afbc80ee53
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -0,0 +1,373 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "dmi.h"
+
+extern unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+void generate_cpu_entries(void); // from cpu/intel/speedstep
+unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
+
+#define OLD_ACPI 0
+#if OLD_ACPI
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset (gnvs, 0, sizeof(global_nvs_t));
+
+	gnvs->LIDS = 1;
+	gnvs->PWRS = 1;
+
+	gnvs->ACTT = 0x37;
+	gnvs->PSVT = 0x4f;
+
+	gnvs->TC1V = 0x00;
+	gnvs->TC2V = 0x0a;
+	gnvs->TSPV = 0x02;
+
+	gnvs->CRTT = 0x77;
+
+	gnvs->B0SC = 0x54;
+	gnvs->APIC = 0x01;
+	gnvs->MPEN = 0x01;
+
+	gnvs->PPCM = 0x02;
+	gnvs->PCP0 = 0xbf;
+	gnvs->PCP1 = 0xbf;
+
+	gnvs->CMAP = 0x01;
+	gnvs->CMBP = 0x01;
+	gnvs->LT0  = 0x01;
+	gnvs->FDCP = 0x01;
+	gnvs->CMCP = 0x01;
+	gnvs->CMDP = 0x01;
+	gnvs->P2M  = 0x02;
+
+	gnvs->IGDS = 0x01;
+
+	gnvs->CADL = 0x09;
+	gnvs->PADL = 0x09;
+
+	gnvs->NDID = 3;
+	gnvs->DID1 = 0x80000100;
+	gnvs->DID2 = 0x80000240;
+	gnvs->DID3 = 0x80000410;
+	gnvs->DID4 = 0x80000410;
+	gnvs->DID5 = 0x00000005;
+
+	gnvs->ALAF = 0x64;
+	gnvs->LLOW = 0x2c;
+	gnvs->LHIH = 0x01;
+
+        // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
+	// oemb->topm = tolud;
+}
+#endif
+
+#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+
+	/* Enable both COM ports */
+	gnvs->cmap = 0x01;
+	gnvs->cmbp = 0x01;
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+}
+
+void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header = &(hpet->header);
+	acpi_addr_t *addr = &(hpet->addr);
+
+	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	addr->space_id = 0;	/* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = HPET_ADDR & 0xffffffff;
+	addr->addrh = HPET_ADDR >> 32;
+
+	hpet->id = 0x8086a201;	/* Intel */
+	hpet->number = 0x00;
+	hpet->min_tick = 0x0080;
+
+	header->checksum =
+	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+
+
+#define IO_APIC_ADDR	0xfec00000UL
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* LAPIC_NMI */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 0,
+				MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 1, MP_IRQ_POLARITY_HIGH | 
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
+
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+	void *gnvs;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk_debug("ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk_debug("ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk_debug("ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk_debug("ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	current += ((acpi_header_t *) AmlCode)->length;
+	memcpy((void *) dsdt, (void *) AmlCode,
+	       ((acpi_header_t *) AmlCode)->length);
+
+	/* Fix up global NVS region for SMI handler. The GNVS region lives 
+	 * in the (high) table area. The low memory map looks like this:
+	 *
+	 * 0x00000000 - 0x000003ff	Real Mode IVT
+	 * 0x00000020 - 0x0000019c	Low MP Table (XXX conflict?)
+	 * 0x00000400 - 0x000004ff	BDA (somewhat unused)
+	 * 0x00000500 - 0x0000052f	Moved GDT
+	 * 0x00000530 - 0x00000b64	coreboot table
+	 * 0x0007c000 - 0x0007dfff	OS boot sector (unused?)
+	 * 0x0007e000 - 0x0007ffff	free to use (so no good for acpi+smi)
+	 * 0x00080000 - 0x0009fbff	usable ram
+	 * 0x0009fc00 - 0x0009ffff	EBDA (unused?)
+	 * 0x000a0000 - 0x000bffff	VGA memory
+	 * 0x000c0000 - 0x000cffff	VGA option rom
+	 * 0x000d0000 - 0x000dffff	free for other option roms?
+	 * 0x000e0000 - 0x000fffff	SeaBIOS? (conflict with low tables:)
+	 * 0x000f0000 - 0x000f03ff	PIRQ table
+	 * 0x000f0400 - 0x000f66??	ACPI tables
+	 * 0x000f66?? - 0x000f????	DMI tables
+	 */
+
+	ALIGN_CURRENT;
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* Keep pointer around */
+	gnvs = (void *)current;
+
+	current += 0x100;
+	ALIGN_CURRENT;
+
+	/* And tell SMI about it */
+	smm_setup_structures(gnvs, NULL, NULL);
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk_debug("ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk_debug("ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk_debug("ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk_debug("ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk_debug("current = %lx\n", current);
+
+	printk_debug("ACPI:     * DMI (Linux workaround)\n");
+	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
+#if CONFIG_WRITE_HIGH_TABLES == 1
+	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
+	current += DMI_TABLE_SIZE;
+	ALIGN_CURRENT;
+#endif
+
+	printk_info("ACPI: done.\n");
+
+	/* Enable Dummy DCC ON# for DVI */
+	printk_debug("Laptop handling...\n");
+	outb(inb(0x60f) & ~(1 << 5), 0x60f);
+
+	return current;
+}
diff --git a/src/mainboard/roda/rk886ex/auto.c b/src/mainboard/roda/rk886ex/auto.c
new file mode 100644
index 0000000000..868d41edff
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/auto.c
@@ -0,0 +1,403 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+#define __PRE_RAM__
+
+/* Configuration of the i945 driver */
+#define CHIPSET_I945GM 1
+#define CHANNEL_XOR_RANDOMIZATION 1
+// Rocky freezing temperature settings:
+#define MAXIMUM_SUPPORTED_FREQUENCY 400
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include <cpu/x86/bist.h>
+
+#if CONFIG_USBDEBUG_DIRECT
+#define DBGP_DEFAULT 1
+#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+
+#include "northbridge/intel/i945/udelay.c"
+
+#include "southbridge/intel/i82801gx/i82801gx.h"
+static void setup_ich7_gpios(void)
+{
+	printk_debug(" GPIOS...");
+	/* General Registers */
+	outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
+	outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
+	outl(0x7dc07f83, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	/* Output Control Registers */
+	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
+	/* Input Control Registers */
+	outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
+	outl(0x000100e8, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
+	outl(0x00000030, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
+	outl(0x00010030, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
+}
+
+#include "northbridge/intel/i945/early_init.c"
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i945/raminit.h"
+#include "northbridge/intel/i945/raminit.c"
+#include "northbridge/intel/i945/reset_test.c"
+#include "northbridge/intel/i945/errata.c"
+#include "northbridge/intel/i945/debug.c"
+
+static void ich7_enable_lpc(void)
+{
+	// Enable Serial IRQ
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	// decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+	// decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+	// Enable 0x02e0
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
+	// COM3 decode
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
+	// COM4 decode
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
+}
+
+
+/* This box has two superios, so enabling serial becomes slightly excessive.
+ * We disable a lot of stuff to make sure that there are no conflicts between
+ * the two. Also set up the GPIOs from the beginning. This is the "no schematic
+ * but safe anyways" method.
+ */
+static inline void pnp_enter_ext_func_mode(device_t dev)
+{
+	unsigned int port = dev >> 8;
+	outb(0x55, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	unsigned int port = dev >> 8;
+	outb(0xaa, port);
+}
+
+static void pnp_write_register(device_t dev, int reg, int val)
+{
+	unsigned int port = dev >> 8;
+	outb(reg, port);
+	outb(val, port+1);
+}
+
+static void early_superio_config(void)
+{
+	device_t dev;
+
+	dev=PNP_DEV(0x2e, 0x00);
+
+	pnp_enter_ext_func_mode(dev);
+	pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
+	pnp_write_register(dev, 0x02, 0x88); // UART power on
+	pnp_write_register(dev, 0x03, 0x72); // Floppy
+	pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
+	pnp_write_register(dev, 0x14, 0x03); // Floppy
+	pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
+	pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
+	pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
+	pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
+	pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
+	pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
+	pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
+	/* These are the SMI status registers in the SIO: */
+	pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
+
+	pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
+	pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
+	pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
+	pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
+	pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
+	pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
+	pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
+	pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
+	pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
+
+	pnp_exit_ext_func_mode(dev);
+}
+
+static void rcba_config(void)
+{
+	/* Set up virtual channel 0 */
+	//RCBA32(0x0014) = 0x80000001;
+	//RCBA32(0x001c) = 0x03128010;
+
+	/* Device 1f interrupt pin register */
+	RCBA32(0x3100) = 0x00042220;
+	/* Device 1d interrupt pin register */
+	RCBA32(0x310c) = 0x00214321;
+
+	/* dev irq route register */
+	RCBA16(0x3140) = 0x0232;
+	RCBA16(0x3142) = 0x3246;
+	RCBA16(0x3144) = 0x0237;
+	RCBA16(0x3146) = 0x3201;
+	RCBA16(0x3148) = 0x3216;
+
+	/* Enable IOAPIC */
+	RCBA8(0x31ff) = 0x03;
+
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(0x3400) = (1 << 2);
+
+	/* Disable unused devices */
+	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | 
+			 FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
+	RCBA32(0x3418) |= (1 << 0); // Required.
+
+	/* Enable PCIe Root Port Clock Gate */
+	// RCBA32(0x341c) = 0x00000001;
+
+	/* This should probably go into the ACPI OS Init trap */
+
+	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
+	RCBA32(0x1e84) = 0x00020001;
+	RCBA32(0x1e80) = 0x0000fe01;
+
+	/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+	RCBA32(0x1e9c) = 0x000200f0;
+	RCBA32(0x1e98) = 0x000c0801;
+}
+
+static void early_ich7_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	RCBA32(0x0214) = 0x10030549;
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(0x3418) |= (1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+
+	// next step only on ich7m b0 and later:
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+}
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+#include "southbridge/intel/i82801gx/cmos_failover.c"
+#endif
+
+static void init_artec_dongle(void)
+{
+	// Enable 4MB decoding
+	outb(0xf1, 0x88);
+	outb(0xf4, 0x88);
+}
+
+#include <cbmem.h>
+
+// Now, this needs to be included because it relies on the symbol
+// __PRE_RAM__ being set during CAR stage (in order to compile the 
+// BSS free versions of the functions). Either rewrite the code
+// to be always BSS free, or invent a flag that's better suited than
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
+//
+#include "lib/cbmem.c"
+
+void real_main(unsigned long bist)
+{
+	u32 reg32;
+	int boot_mode = 0;
+
+	if (bist == 0) {
+		enable_lapic();
+	}
+
+	ich7_enable_lpc();
+	early_superio_config();
+
+	/* Set up the console */
+	uart_init();
+
+#if CONFIG_USBDEBUG_DIRECT
+	i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+#endif
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk_debug("soft reset detected.\n");
+		boot_mode = 1;
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i945_early_initialization();
+
+	/* This has to happen after i945_early_initialization() */
+	init_artec_dongle();
+
+	/* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk_debug("PM1_CNT: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk_debug("Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+
+#else
+		printk_debug("Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+	
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	dump_spd_registers();
+#endif
+
+	sdram_initialize(boot_mode);
+
+	/* Perform some initialization that must run before stage2 */
+	early_ich7_init();
+
+	/* This should probably go away. Until now it is required 
+	 * and mainboard specific 
+	 */
+	rcba_config();
+
+	/* Chipset Errata! */
+	fixup_i945_errata();
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	i945_late_initialization();
+
+#if !CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+#if defined(DEBUG_RAM_SETUP)
+	sdram_dump_mchbar_registers();
+
+	{
+		/* This will not work if TSEG is in place! */
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+
+		printk_debug("TOM: 0x%08x\n", tom);
+		ram_check(0x00000000, 0x000a0000);
+		ram_check(0x00100000, tom);
+	}
+#endif
+#endif
+#endif
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Start address of high memory tables */
+	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+		 * through stage 2. We could keep stuff like stack and heap in high tables
+		 * memory completely, but that's a wonderful clean up task for another
+		 * day.
+		 */
+		if (resume_backup_memory) 
+			memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	}
+#endif
+}
+
+#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/roda/rk886ex/chip.h
new file mode 100644
index 0000000000..17c6f00905
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/chip.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {
+	int nothing;
+};
diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout
new file mode 100644
index 0000000000..985aa14275
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/cmos.layout
@@ -0,0 +1,144 @@
+#
+# This file is part of the coreboot project.
+# 
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+#409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+#928         80       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# ram initialization internal data
+1024         8       r       0        C0WL0REOST
+1032         8       r       0        C1WL0REOST
+1040         8       r       0        RCVENMT
+1048         4       r       0        C0DRT1
+1052         4       r       0        C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
new file mode 100644
index 0000000000..b578e19a55
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -0,0 +1,115 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i945
+
+        device apic_cluster 0 on
+                chip cpu/intel/socket_mFCPGA478
+                        device apic 0 on end
+                end
+        end
+
+        device pci_domain 0 on 
+                device pci 00.0 on end # host bridge
+		# auto detection:
+		#device pci 01.0 off end # i945 PCIe root port
+		#device pci 02.0 on end # vga controller
+		#device pci 02.1 on end # display controller
+
+                chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x0b"
+			register "pirqh_routing" = "0x0b"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "2"
+			register "gpi8_routing"  = "1"
+			register "gpi7_routing"  = "2"
+			register "gpe0_en" = "0x20800007"
+
+                        register "ide_legacy_combined" = "0x1"
+                        register "ide_enable_primary" = "0x1"
+                        register "ide_enable_secondary" = "0x0"
+                        register "sata_ahci" = "0x0"
+
+                	device pci 1b.0 on end # High Definition Audio
+                	device pci 1c.0 on end # PCIe
+                	device pci 1c.1 on end # PCIe
+                	device pci 1c.2 on end # PCIe
+			#device pci 1c.3 off end # PCIe port 4
+			#device pci 1c.4 off end # PCIe port 5
+			#device pci 1c.5 off end # PCIe port 6
+                	device pci 1d.0 on end # USB UHCI
+                	device pci 1d.1 on end # USB UHCI
+                	device pci 1d.2 on end # USB UHCI
+                	device pci 1d.3 on end # USB UHCI
+                	device pci 1d.7 on end # USB2 EHCI
+                	device pci 1e.0 on
+				chip southbridge/ti/pci7420
+                        		register "smartcard_enabled" = "0x0"
+					device pci 3.0 on end
+					device pci 3.1 on end
+					device pci 3.2 on end
+					device pci 3.3 off end  # smartcard
+				end
+			end # PCI bridge
+			#device pci 1e.2 off end # AC'97 Audio 
+			#device pci 1e.3 off end # AC'97 Modem
+                        device pci 1f.0 on # LPC bridge
+                                chip superio/smsc/lpc47n227
+					device pnp 2e.1 off # Parallel port
+					end
+					device pnp 2e.2 on # COM1
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+					end
+					device pnp 2e.3 on # COM2
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+					end
+					device pnp 2e.5 off # Keyboard+Mouse
+					#	 io 0x60 = 0x60
+					#	 io 0x62 = 0x64
+					#	irq 0x70 = 1
+					#	irq 0x72 = 12
+					end
+                                end
+				chip superio/renesas/m3885x
+					device pnp ff.1 on # dummy address
+					end
+				end
+
+                        end
+			#device pci 1f.1 off end # IDE
+                        device pci 1f.2 on end  # SATA
+                        device pci 1f.3 on end  # SMBus
+			#device pci 1f.4 off end # Realtek ID Codec
+                end
+        end
+end
diff --git a/src/mainboard/roda/rk886ex/dmi.h b/src/mainboard/roda/rk886ex/dmi.h
new file mode 100644
index 0000000000..692949a0e7
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/dmi.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define DMI_TABLE_SIZE 0x55
+
+static u8 dmi_table[DMI_TABLE_SIZE] = {
+	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
+	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
+	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
+	0x30, 0x30, 0x38, 0x00, 0x00
+};
diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl
new file mode 100644
index 0000000000..67539cce53
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/dsdt.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv2",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl"
+
+	// General Purpose Events
+	#include "acpi/gpe.asl"
+	
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+	// Thermal Zone
+	#include "acpi/thermal.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include "../../../northbridge/intel/i945/acpi/i945.asl"
+			#include "../../../southbridge/intel/i82801gx/acpi/ich7.asl"
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl"
+}
diff --git a/src/mainboard/roda/rk886ex/ec.c b/src/mainboard/roda/rk886ex/ec.c
new file mode 100644
index 0000000000..5121ac2e08
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/ec.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "ec.h"
+
+int send_ec_command(u8 command)
+{
+	int timeout;
+
+	timeout = 0x7ff;
+	while ((inb(EC_SC) & EC_IBF) && --timeout) {
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk_spew(".");
+	}
+	if (!timeout) {
+		printk_debug("Timeout while sending command 0x%02x to EC!\n", 
+				command);
+		// return -1;
+	}
+
+	outb(command, EC_SC);
+	return 0;
+}
+
+int send_ec_data(u8 data)
+{
+	int timeout;
+
+	timeout = 0x7ff;
+	while ((inb(EC_SC) & EC_IBF) && --timeout) { // wait for IBF = 0
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk_spew(".");
+	}
+	if (!timeout) {
+		printk_debug("Timeout while sending data 0x%02x to EC!\n",
+				data);
+		// return -1;
+	}
+
+	outb(data, EC_DATA);
+
+	return 0;
+}
+
+int send_ec_data_nowait(u8 data)
+{
+	outb(data, EC_DATA);
+
+	return 0;
+}
+
+u8 recv_ec_data(void)
+{
+	int timeout;
+	u8 data;
+
+	timeout = 0x7fff;
+	while (--timeout) { // Wait for OBF = 1
+		if (inb(EC_SC) & EC_OBF) {
+			break;
+		}
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk_spew(".");
+	}
+	if (!timeout) {
+		printk_debug("\nTimeout while receiving data from EC!\n");
+		// return -1;
+	}
+
+	data = inb(EC_DATA);
+	printk_debug("recv_ec_data: 0x%02x\n", data);
+
+	return data;
+}
+
+u8 ec_read(u8 addr)
+{
+	send_ec_command(0x80);
+	send_ec_data(addr);
+
+	return recv_ec_data();
+}
+
+int ec_write(u8 addr, u8 data)
+{
+	send_ec_command(0x81);
+	send_ec_data(addr);
+	return send_ec_data(data);
+}
+
diff --git a/src/mainboard/roda/rk886ex/ec.h b/src/mainboard/roda/rk886ex/ec.h
new file mode 100644
index 0000000000..a4565e24a9
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/ec.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _MAINBOARD_EC_H
+#define _MAINBOARD_EC_H
+
+#define EC_DATA	0x62
+#define EC_SC	0x66
+
+/* EC_SC input */
+#define   EC_SMI_EVT	(1 << 6) // 1: SMI event pending
+#define   EC_SCI_EVT	(1 << 5) // 1: SCI event pending
+#define   EC_BURST	(1 << 4) // controller is in burst mode
+#define   EC_CMD	(1 << 3) // 1: byte in data register is command
+				 // 0: byte in data register is data
+#define   EC_IBF	(1 << 1) // 1: input buffer full (data ready for ec)
+#define   EC_OBF	(1 << 0) // 1: output buffer full (data ready for host)
+/* EC_SC output */
+#define   RD_EC		0x80 // Read Embedded Controller
+#define   WR_EC		0x81 // Write Embedded Controller
+#define   BE_EC		0x82 // Burst Enable Embedded Controller
+#define   BD_EC 	0x83 // Burst Disable Embedded Controller
+#define   QR_EC 	0x84 // Query Embedded Controller
+
+int send_ec_command(u8 command);
+int send_ec_data(u8 data);
+int send_ec_data_nowait(u8 data);
+u8 recv_ec_data(void);
+u8 ec_read(u8 addr);
+int ec_write(u8 addr, u8 data);
+
+#endif
+
diff --git a/src/mainboard/roda/rk886ex/fadt.c b/src/mainboard/roda/rk886ex/fadt.c
new file mode 100644
index 0000000000..e45db8a351
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/fadt.c
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 0x00;
+	fadt->preferred_pm_profile = PM_MOBILE;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = ACPI_ENABLE;
+	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x20;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 0x23;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x32;
+	fadt->iapc_boot_arch = 0x00;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_DOCKING_SUPPORTED;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 0;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 0;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 0;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c
new file mode 100644
index 0000000000..6aa36bf026
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/irq_tables.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*18,	 /* There can be total 18 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0,		 /* IRQs devoted exclusively to PCI usage */
+	0x8086,		 /* Vendor */
+	0x27b0,		 /* Device */
+	0,		 /* miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xf,		 /* u8 checksum. */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+		{0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+		{0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+		{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+		{0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+		{0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+		{0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+		{0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+		{0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+		{0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+		{0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+		{0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+		{0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+		{0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+		{0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+		{0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+		{0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+		{0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
+
diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c
new file mode 100644
index 0000000000..66e030da88
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/m3885.c
@@ -0,0 +1,417 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <delay.h>
+
+#include "ec.h"
+#include "m3885.h"
+
+#define TH0LOW	80
+#define TH0HIGH	85
+#define TH0CRIT	120
+#define TH1LOW	75
+#define TH1HIGH	80
+
+static u8 variables[] = {
+     /* Offs,  AND,   OR */
+	0x08, 0x48, 0x6C,  // Keyboard ScanCode Set & LED Data (kState1)
+	0x0a, 0x01, 0x00,  // Keyboard Shift flags (kState3)
+	0x0c, 0x80, 0x08,  // Keyboard State flags (kState5)
+	0x11, 0xff, 0x06,  // Make/Break Debounce #'s (debounce)
+	0x13, 0xff, 0x00,  // HotKey1 ScanCode (hotKey1)
+	0x14, 0xff, 0x00,  // HotKey2 ScanCode (hotKey2)
+	0x15, 0xff, 0x3f,  // HotKey3 ScanCode (hotKey3)
+	0x16, 0xff, 0x00,  // HotKey4 ScanCode (hotKey4)
+	0x17, 0xff, 0x00,  // HotKey5 ScanCode (hotKey5)
+	0x18, 0xff, 0x0e,  // HotKey6 ScanCode (hotKey6)
+	0x19, 0xff, 0x9f,  // HotKey1 Task = c5 Command Data (keyTsk1)
+	0x1a, 0xff, 0x9f,  // HotKey2 Task = c5 Command Data (keyTsk2)
+	0x1b, 0xff, 0x6a,  // HotKey3 Task = c5 Command Data (keyTsk3)
+	0x1c, 0xff, 0x9f,  // HotKey4 Task = c5 Command Data (keyTsk4)
+	0x1d, 0xff, 0x9f,  // HotKey5 Task = c5 Command Data (keyTsk5)
+	0x1e, 0xff, 0x87,  // FuncKey Task = c5 Command Data (funcTsk)
+	0x1f, 0xff, 0x9f,  // Delayed Task = c5 Command Data (dlyTsk1)
+	0x20, 0xff, 0x9f,  // Wake-Up Task = c5 Command Data (wakeTsk)
+	// 
+	0x21, 0xff, 0x08,  // WigglePin Pulse Width * 2.4ms (tmPulse)
+	0x24, 0xff, 0x30,  // Keyboard State Flags (kState7)
+	//
+	0x2b, 0xff, 0x00,  //
+	0x2c, 0xff, 0x80,  // Set Fn-Key 8
+	0x2d, 0xff, 0x02,  // Set Fn-Key 9
+	0x2e, 0xff, 0x00,  // Set Fn-Key 1-8 task  (0 = SMI)
+	0x2f, 0xff, 0x00,  // Set Fn-Key 9-12 task (1 = SCI)
+};
+
+static u8 matrix[] = {
+	0xc1,0xc0,0xd8,0xdb,0xbf,0x05,0x76,0xbf,  // (0x00-0x07)
+	0xbf,0x80,0x78,0xbf,0xbf,0x07,0x88,0xc2,  // (0x08-0x0f)
+	0x03,0x09,0xd9,0x16,0xbf,0x06,0x0e,0x81,  // (0x10-0x17)
+	0xbf,0xbf,0xee,0xbf,0xbf,0x55,0x9a,0x89,  // (0x18-0x1f)
+	0x1e,0x15,0x36,0xda,0xe8,0xbf,0x0d,0xbf,  // (0x20-0x27)
+	0xbf,0xbf,0xbf,0xa3,0xbf,0x4e,0x66,0x8b,  // (0x28-0x2f)
+	0x1d,0x2e,0xe6,0xe7,0xe5,0x1c,0x58,0xbf,  // (0x30-0x37)
+	0x82,0xbf,0xf0,0xbf,0xbf,0x5b,0x5d,0x8c,  // (0x38-0x3f)
+	0x22,0x25,0x2c,0x35,0xe1,0x1a,0x96,0xbf,  // (0x40-0x47)
+	0xbf,0xbf,0xec,0xbf,0xbf,0x54,0xf1,0x8f,  // (0x48-0x4f)
+	0x1b,0x2a,0x2b,0x32,0xe9,0x31,0x29,0x61,  // (0x50-0x57)
+	0xbf,0xbf,0x8d,0xbf,0x86,0xc3,0x92,0x93,  // (0x58-0x5f)
+	0x21,0x23,0x34,0x33,0x41,0xe0,0xbf,0xbf,  // (0x60-0x67)
+	0xbf,0x85,0xeb,0xbf,0xb6,0xbf,0x91,0xbf,  // (0x68-0x6f)
+	0x26,0x24,0x2d,0xe3,0xe2,0xe4,0xbf,0xbf,  // (0x70-0x77)
+	0x87,0xbf,0xea,0xbf,0xbf,0x52,0x90,0x8e,  // (0x78-0x7f)
+};
+
+static u8 function_ram[] = {
+	0x04,0xbd,0x0c,0xbe,0x7e,0x9a,0x8a,0xb6,  // (0xc0-0xc3)
+	0x92,0x8f,0x93,0x8e,0x81,0x86,0x82,0x87,  // (0xc4-0xc7)
+	0x8a,0x9a,0x8d,0x7e,0x88,0x84,0x7e,0x78,  // (0xc8-0xcb)
+	0x77,0x07,0x77,0x98,0x89,0xb2,0x05,0x9b,  // (0xcc-0xcf)
+	0x78,0x84,0x07,0x88,0x8a,0x7e,0x05,0xa6,  // (0xd0-0xd3)
+	0x06,0xa7,0x04,0xa8,0x0c,0xa9,0x03,0xaa,  // (0xd4-0xd7)
+	0x0b,0xc1,0x83,0xc0,0x0a,0xad,0x01,0xae,  // (0xd8-0xdb)
+	0x09,0xaf,0x78,0xb0,0x07,0xb1,0x1a,0x61,  // (0xdc-0xdf)
+	0x3b,0x69,0x42,0x72,0x4b,0x7a,0x3c,0x6b,  // (0xe0-0xe3)
+	0x43,0x73,0x44,0x74,0x3d,0x6c,0x3e,0x75,  // (0xe4-0xe7)
+	0x46,0x7d,0x3a,0x70,0x49,0x71,0x4a,0x94,  // (0xe8-0xeb)
+	0x4c,0x79,0x4c,0x7c,0x45,0x7c,0x45,0x79,  // (0xec-0xef)
+	0x4d,0x7b,0x5a,0x95,0x4c,0x7b,0x45,0x7b,  // (0xf0-0xf3)
+	0x4d,0x79,0x4d,0x7c,0x4e,0x7b,0x54,0x95,  // (0xf4-0xf7)
+	0x52,0x7c,0x45,0x94,0x4a,0x79,0xb3,0x95,  // (0xf8-0xfb)
+	0xb4,0x7b,0xb5,0x7c,0x00,0x00,0x55,0x79,  // (0xfc-0xff)
+};
+
+
+#define KBD_DATA	0x60
+#define KBD_SC		0x64
+
+#define   KBD_IBF	(1 << 1) // 1: input buffer full (data ready for ec)
+#define   KBD_OBF	(1 << 0) // 1: output buffer full (data ready for host)
+
+static int send_kbd_command(u8 command)
+{
+	int timeout;
+
+	timeout = 0x7ff;
+	while ((inb(KBD_SC) & KBD_IBF) && --timeout) {
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk_spew(".");
+	}
+	if (!timeout) {
+		printk_debug("Timeout while sending command 0x%02x to EC!\n", 
+				command);
+		// return -1;
+	}
+
+	outb(command, KBD_SC);
+	return 0;
+}
+
+static int send_kbd_data(u8 data)
+{
+	int timeout;
+
+	timeout = 0x7ff;
+	while ((inb(KBD_SC) & KBD_IBF) && --timeout) { // wait for IBF = 0
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk_spew(".");
+	}
+	if (!timeout) {
+		printk_debug("Timeout while sending data 0x%02x to EC!\n",
+				data);
+		// return -1;
+	}
+
+	outb(data, KBD_DATA);
+
+	return 0;
+}
+
+
+static u8 recv_kbd_data(void)
+{
+	int timeout;
+	u8 data;
+
+	timeout = 0x7fff;
+	while (--timeout) { // Wait for OBF = 1
+		if (inb(KBD_SC) & KBD_OBF) {
+			break;
+		}
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk_spew(".");
+	}
+	if (!timeout) {
+		printk_debug("\nTimeout while receiving data from EC!\n");
+		// return -1;
+	}
+
+	data = inb(KBD_DATA);
+
+	return data;
+}
+
+
+static u8 m3885_get_variable(u8 index)
+{
+	u8 ret;
+
+	send_kbd_command(0xb8);
+	send_kbd_data(index);
+	send_kbd_command(0xbc);
+	send_kbd_command(0xff);
+	ret = recv_kbd_data();
+	printk_spew("m3885: get variable %02x = %02x\n", index, ret);
+	return ret;
+}
+
+static void m3885_set_variable(u8 index, u8 data)
+{
+	printk_spew("m3885: set variable %02x = %02x\n", index, data);
+	send_kbd_command(0xb8);
+	send_kbd_data(index);
+	send_kbd_command(0xbd);
+	send_kbd_data(data);
+}
+
+static void m3885_set_proc_ram(u8 index, u8 data)
+{
+	printk_spew("m3885: set procram %02x = %02x\n", index, data);
+	send_kbd_command(0xb8);
+	send_kbd_data(index);
+	send_kbd_command(0xbb);
+	send_kbd_data(data);
+}
+
+static u8 m3885_get_proc_ram(u8 index)
+{
+	u8 ret;
+
+	send_kbd_command(0xb8);
+	send_kbd_data(index);
+	send_kbd_command(0xba);
+	// send_kbd_command(0xff);
+	ret = recv_kbd_data();
+	printk_spew("m3885: get procram %02x = %02x\n", index, ret);
+	return ret;
+}
+
+static u8 m3885_read_port(void)
+{
+	u8 reg8;
+
+	reg8 = m3885_get_variable(0x0c);
+	reg8 &= ~(7 << 4);
+	reg8 |= (4 << 4);	// bank 4
+	m3885_set_variable(0x0c, reg8);
+
+	/* P6YSTATE */
+	return m3885_get_proc_ram(0xf8);
+}
+
+void m3885_configure_multikey(void)
+{
+	int i;
+	u8 reg8;
+	u8 kstate5_flags, offs, maxvars;
+
+	/* ram bank 0 */
+	kstate5_flags = m3885_get_variable(0x0c);
+	m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4));
+
+	/* Write Matrix to bank 0 */
+	for (i=0; i < ARRAY_SIZE(matrix); i++) {
+		m3885_set_proc_ram(i + 0x80, matrix[i]);
+	}
+
+	
+	/* ram bank 2 */
+	m3885_set_variable(0x0c, (kstate5_flags & (~(7 << 4))) | (2 << 4));
+
+	/* Get the number of variables */
+	maxvars = m3885_get_variable(0x00);
+	printk_debug("M388x has %d variables in bank 2.\n", maxvars);
+	if (maxvars >= 35) {
+		offs = m3885_get_variable(0x23);
+		if ((offs > 0xc0) || (offs < 0x80)) {
+			printk_debug("M388x does not have a valid ram offset (0x%x)\n", offs);
+		} else {
+			printk_debug("Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
+			for (i=0; i < ARRAY_SIZE(function_ram); i++) {
+				m3885_set_proc_ram(i + offs, function_ram[i]);
+			}
+		}
+	} else {
+		printk_debug("Could not load Function-RAM (%d).\n", maxvars);
+	}
+
+	// restore original bank
+	m3885_set_variable(0x0c, kstate5_flags);
+	maxvars = m3885_get_variable(0x00);
+	printk_debug("M388x has %d variables in original bank.\n", maxvars);
+	for (i=0; i<ARRAY_SIZE(variables); i+=3) {
+		u8 reg8;
+		if(variables[i + 0] > maxvars)
+			continue;
+		reg8 = m3885_get_variable(variables[i + 0]);
+		reg8 &= ~(variables[i + 1]);
+		reg8 |= variables[i + 2]; //  & ~variables[i + 1];
+		m3885_set_variable(variables[i + 0], reg8);
+	}
+
+	/* OEM Init */
+
+	/* Set Bank 1 */
+	m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (1 << 4));
+
+	/* Set SMI# at P5.1 */
+	/* SMI Control -> p5.1 = EXTSMI# */
+	m3885_set_proc_ram(0xff, 0xc1);
+
+	/* Set Fn-Key Task 0 -> SMI#/SCI */
+	m3885_set_proc_ram(0x6d, 0x81);
+
+	/* Set Fn-Key Task 1 -> SCI */
+	m3885_set_proc_ram(0x6c, 0x80);
+
+	/* Number of Thermal Sensors */
+	m3885_set_proc_ram(0xf2, 0x02);
+
+	/* Critical Task */
+	m3885_set_proc_ram(0xf3, 0x5d);
+	
+	/* Thermal Polling Period */
+	m3885_set_proc_ram(0xf9, 0x0a);
+
+	/* ReadPort */
+	// m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (4 << 4));
+
+	/* AC PRESN# */
+	if (m3885_read_port() & (1 << 0))
+		reg8 = 0x8a;
+	else
+		reg8 = 0x9a;
+	m3885_set_proc_ram(0xd0, reg8); // P60SPEC
+	
+	/* SENSE1# */
+	if (m3885_read_port() & (1 << 2))
+		reg8 = 0x8a;
+	else
+		reg8 = 0x9a;
+	m3885_set_proc_ram(0xd2, reg8); // P62SPEC
+	
+	/* SENSE2# */
+	if (m3885_read_port() & (1 << 3))
+		reg8 = 0x8a;
+	else
+		reg8 = 0x9a;
+	m3885_set_proc_ram(0xd3, reg8); // P63SPEC
+	
+	/* Low Active Port */
+	m3885_set_proc_ram(0xd1, 0x88); // P61SPEC
+	m3885_set_proc_ram(0xd6, 0x88); // P66SPEC
+	m3885_set_proc_ram(0xd7, 0x88); // P67SPEC
+
+	/* High Active Port */
+	m3885_set_proc_ram(0xd4, 0x98); // P64SPEC
+	m3885_set_proc_ram(0xd5, 0x98); // P65SPEC
+
+	/* Set P60TASK-P67TASK */
+	/* SCI */
+	m3885_set_proc_ram(0xda, 0x80); // P62TASK SENSE1#
+	m3885_set_proc_ram(0xdb, 0x80); // P63TASK SENSE2#
+	m3885_set_proc_ram(0xdd, 0x80); // P65TASK PROCHOT
+	m3885_set_proc_ram(0xde, 0x80); // P65TASK THERMTRIP#
+	m3885_set_proc_ram(0xdf, 0x80); // P65TASK PME#
+	/* SMI/SCI */
+	m3885_set_proc_ram(0xd8, 0x81); // P60TASK, AC_PRESN#
+	m3885_set_proc_ram(0xd9, 0x81); // P61TASK, LID#
+	m3885_set_proc_ram(0xdc, 0x81); // P64TASK, FDD/LPT#
+
+	/* Thermal */
+	/* Bank 5 */
+	m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (5 << 4));
+
+	/* Thermal 0: Active cooling, Speed Step Down */
+	m3885_set_proc_ram(0x81, 0x9c);    // THRM0
+	m3885_set_proc_ram(0x82, 0x01);    // THRM0 CMD
+	m3885_set_proc_ram(0x84, TH0LOW);  // THRM0 LOW
+	m3885_set_proc_ram(0x85, TH0HIGH); // THRM0 HIGH
+	m3885_set_proc_ram(0x86, 0x81);    // Set Task SMI#/SCI
+	m3885_set_proc_ram(0x87, TH0CRIT); // THRM0 CRIT
+
+	/* Thermal 1: Passive cooling, Fan On */
+	m3885_set_proc_ram(0x89, 0x9c);    // THRM1
+	m3885_set_proc_ram(0x8a, 0x01);    // THRM1 CMD
+	m3885_set_proc_ram(0x8c, TH1LOW);  // THRM1 LOW
+	m3885_set_proc_ram(0x8d, TH1HIGH); // THRM1 HIGH
+	m3885_set_proc_ram(0x8e, 0x81);    // Set Task SMI#/SCI
+
+	/* Switch Task to SMI */
+	udelay(100 * 1000); // 100ms
+	outb(KBD_SC, 0xca);
+	udelay(100 * 1000); // 100ms
+	outb(KBD_DATA, 0x17);
+
+	/* Set P22 to high level, keyboard backlight default off */
+	udelay(100 * 1000); // 100ms
+	outb(KBD_SC, 0xc5);
+	udelay(100 * 1000); // 100ms
+	outb(KBD_DATA, 0x4a);
+}
+
+u8 m3885_gpio(u8 value)
+{
+#if 0
+	int timeout;
+#endif
+
+	/* First write data */
+	ec_write(M3885_CMDAT1, value);
+
+	/* Issue command: ACCESS GPIO */
+	ec_write(M3885_CMCMD, 0xc5);
+
+#if 0
+	/* CMCMD is 0 when the command is completed */
+	timeout = 0xf;
+	while (ec_read(M3885_CMCMD) && --timeout) {
+		udelay(10);
+		printk_debug(".");
+	}
+	if (!timeout) {
+		printk_debug("\nTimeout while waiting for M3885 command!\n");
+	}
+
+	/* If it was a read function: Pin state */
+	return ec_read(M3885_CMDAT1);
+#else
+	return 0;
+#endif
+}
+
diff --git a/src/mainboard/roda/rk886ex/m3885.h b/src/mainboard/roda/rk886ex/m3885.h
new file mode 100644
index 0000000000..27e8ac114f
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/m3885.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _MAINBOARD_M3885_H
+#define _MAINBOARD_M3885_H
+
+#define M3885_CMCMD		0x04
+#define M3885_CMDAT1		0x05
+#define M3885_CMDAT2		0x06
+#define M3885_CMDAT3		0x07
+
+#define M3885_GPIO_LEVEL	(0<<7)
+#define M3885_GPIO_PULSE	(1<<7)
+
+#define M3885_GPIO_READ		(0<<5)
+#define M3885_GPIO_SET		(1<<5)
+#define M3885_GPIO_CLEAR	(2<<5)
+#define M3885_GPIO_TOGGLE	(3<<5)
+
+#define M3885_GPIO_P14		(0x00<<0)
+#define M3885_GPIO_P15		(0x01<<0)
+#define M3885_GPIO_P16		(0x02<<0)
+#define M3885_GPIO_P17		(0x03<<0)
+
+#define M3885_GPIO_P54		(0x04<<0)
+#define M3885_GPIO_P55		(0x05<<0)
+#define M3885_GPIO_P56		(0x06<<0)
+#define M3885_GPIO_P57		(0x07<<0)
+
+#define M3885_GPIO_P20		(0x08<<0)
+#define M3885_GPIO_P21		(0x09<<0)
+#define M3885_GPIO_P22		(0x0a<<0)
+#define M3885_GPIO_P23		(0x0b<<0)
+#define M3885_GPIO_P24		(0x0c<<0)
+#define M3885_GPIO_P25		(0x0d<<0)
+#define M3885_GPIO_P26		(0x0e<<0)
+#define M3885_GPIO_P27		(0x0f<<0)
+
+#define M3885_GPIO_P40		(0x10<<0)
+#define M3885_GPIO_P41		(0x11<<0)
+#define M3885_GPIO_P42		(0x12<<0)
+#define M3885_GPIO_P43		(0x13<<0)
+#define M3885_GPIO_P44		(0x14<<0)
+#define M3885_GPIO_P45		(0x15<<0)
+#define M3885_GPIO_P46		(0x16<<0)
+#define M3885_GPIO_P47		(0x17<<0)
+
+#define M3885_GPIO_P60		(0x18<<0)
+#define M3885_GPIO_P61		(0x19<<0)
+#define M3885_GPIO_P62		(0x1a<<0)
+#define M3885_GPIO_P63		(0x1b<<0)
+#define M3885_GPIO_P64		(0x1c<<0)
+#define M3885_GPIO_P65		(0x1d<<0)
+#define M3885_GPIO_P66		(0x1e<<0)
+#define M3885_GPIO_P67		(0x1f<<0)
+
+void m3885_configure_multikey(void);
+u8 m3885_gpio(u8 value);
+
+#endif
diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c
new file mode 100644
index 0000000000..a82553f126
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/mainboard.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include "chip.h"
+
+#include "ec.h"
+#include "m3885.h"
+
+#define DUMP_RUNTIME_REGISTERS 0
+
+static void backlight_enable(void)
+{
+#if 0
+// Disabled, don't let the X9511 burn out
+	int i;
+
+	/* P56 is Brightness Up, and it needs a Pulse instead of a
+	 * Level
+	 */
+	for (i=0; i < 28; i++) {
+		//m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56);
+		m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56);
+	}
+#endif
+	printk_debug("Display I/O: 0x%02x\n", inb(0x60f));
+}
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+	u8 display_id;
+#define BOOT_DISPLAY_DEFAULT	0
+#define BOOT_DISPLAY_CRT	(1 << 0)
+#define BOOT_DISPLAY_TV		(1 << 1)
+#define BOOT_DISPLAY_EFP	(1 << 2)
+#define BOOT_DISPLAY_LCD	(1 << 3)
+#define BOOT_DISPLAY_CRT2	(1 << 4)
+#define BOOT_DISPLAY_TV2	(1 << 5)
+#define BOOT_DISPLAY_EFP2	(1 << 6)
+#define BOOT_DISPLAY_LCD2	(1 << 7)
+
+	printk_debug("%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f35: /* Boot Display */
+		M.x86.R_AX = 0x005f; // Success
+		M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
+		break;
+	case 0x5f40: /* Boot Panel Type */
+		/* LCD panel type is SIO GPIO40-43 */
+		// display_id = inb(0x60f) & 0x0f;
+		display_id = 3;
+		// M.x86.R_AX = 0x015f; // Supported but failed
+		M.x86.R_AX = 0x005f; // Success
+		M.x86.R_CL = display_id;
+		break;
+	default:
+		/* Interrupt was not handled */
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+
+static void int15_install(void)
+{
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+
+#if DUMP_RUNTIME_REGISTERS
+static void dump_runtime_registers(void)
+{
+	int i;
+
+	printk_debug("SuperIO runtime register block:\n");
+	for (i=0; i<0x10; i++)
+		printk_debug("%02x ", i);
+	printk_debug("\n");
+	for (i=0; i<0x10; i++)
+		printk_debug("%02x ", inb(0x600 +i));
+	printk_debug("\n");
+}
+#endif
+
+static void mainboard_enable(device_t dev) 
+{
+	/* Configure the MultiKey controller */
+	// m3885_configure_multikey();
+
+	/* Enable LCD Backlight */
+	backlight_enable();
+
+	/* Disable Dummy DCC -> GP45 = 1 */
+	outb(inb(0x60f) | (1 << 5), 0x60f);
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
+#if DUMP_RUNTIME_REGISTERS
+	dump_runtime_registers();
+#endif
+}
+
+int add_northbridge_resources(struct lb_memory *mem);
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	return add_northbridge_resources(mem);
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Roda Computer GmbH RK886EX Rugged Notebook (ROCKY3+)")
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/roda/rk886ex/mainboard_smi.c b/src/mainboard/roda/rk886ex/mainboard_smi.c
new file mode 100644
index 0000000000..e0ba6b9d31
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/mainboard_smi.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
+
+/* The southbridge SMI handler checks whether gnvs has a 
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk_debug("Sample\n");
+		//gnvs->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
new file mode 100644
index 0000000000..4764320f48
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <string.h>
+#include <stdint.h>
+
+void *smp_write_config_table(void *v)
+{
+        static const char sig[4] = "PCMP";
+        static const char oem[8] = "COREBOOT";
+        static const char productid[12] = "RK886EX     ";
+        struct mp_config_table *mc;
+	int i;
+	int max_pci_bus, isa_bus;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+        memset(mc, 0, sizeof(*mc));
+
+        memcpy(mc->mpc_signature, sig, sizeof(sig));
+        mc->mpc_length = sizeof(*mc); /* initially just the header */
+        mc->mpc_spec = 0x04;
+        mc->mpc_checksum = 0; /* not yet computed */
+        memcpy(mc->mpc_oem, oem, sizeof(oem));
+        memcpy(mc->mpc_productid, productid, sizeof(productid));
+        mc->mpc_oemptr = 0;
+        mc->mpc_oemsize = 0;
+        mc->mpc_entry_count = 0; /* No entries yet... */
+        mc->mpc_lapic = LAPIC_ADDR;
+        mc->mpe_length = 0;
+        mc->mpe_checksum = 0;
+        mc->reserved = 0;
+
+        smp_write_processors(mc);
+
+	max_pci_bus = 5; // XXX read me from bridges.
+
+	/* ISA bus follows */
+	isa_bus = max_pci_bus + 1;
+
+	/* Bus:		Bus ID	Type */
+	for (i=0; i <= max_pci_bus; i++)
+		smp_write_bus(mc, i, "PCI   ");
+
+	smp_write_bus(mc, isa_bus, "ISA   ");
+
+	/* I/O APICs:	APIC ID	Version	State		Address */
+	smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+
+	/* Legacy Interrupts */
+
+	/* I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */	
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
+
+	/* Builtin devices on Bus 0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
+
+	/* Firewire 4:0.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
+
+	// riser slot top 5:8.0
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
+	// riser slot middle 5:9.0
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
+	// riser slot bottom 5:a.0
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
+
+	/* Onboard Ethernet */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
+
+	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
+	printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/roda/rk886ex/rtl8168.c b/src/mainboard/roda/rk886ex/rtl8168.c
new file mode 100644
index 0000000000..18f41fe32a
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/rtl8168.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This code should work for all ICH* southbridges with a NIC. */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void nic_init(struct device *dev)
+{
+	printk_debug("Initializing RTL8168 Gigabit Ethernet\n");
+	// Nothing to do yet, but this has to be here to keep 
+	// coreboot from trying to execute an option ROM.
+}
+
+static struct device_operations nic_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= nic_init,
+	.scan_bus		= 0,
+};
+
+static const struct pci_driver rtl8169_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= 0x10ec,
+	.device	= 0x8168,
+};
+
+