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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:00:28 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:49:12 +0200 |
| commit | 15fa992cc8467b4cbd8ebea62e3e4c947827137e (patch) | |
| tree | 99e598cc9f4d088a57e04218f2f979a83a6158d6 /src/mainboard/roda | |
| parent | 4c3de9c3edd7cb6fabc72337171862930354f0bf (diff) | |
| download | coreboot-15fa992cc8467b4cbd8ebea62e3e4c947827137e.tar.xz | |
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/roda')
| -rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/roda/rk9/romstage.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index fb06695504..f3af5fa6a0 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -28,6 +28,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -244,8 +245,7 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index ca384260fe..cad75aee1b 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -22,6 +22,7 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> +#include <cpu/intel/romstage.h> #include <arch/acpi.h> #include <cbmem.h> #include <lib.h> @@ -115,8 +116,7 @@ static void default_superio_gpio_setup(void) outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; |